diff options
author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-07-02 23:21:48 +0000 |
---|---|---|
committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-07-02 23:21:48 +0000 |
commit | ff0022d12c12b546287eb0f3cb0b82ac31a15ed3 (patch) | |
tree | 30763c799a47e766cced53aab78029d5b1fb954c | |
parent | 0e6595164d3920a968de274d3b0590a710fad3b2 (diff) |
AMDGPU: Add operand target flags serialization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306995 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/AMDGPU/SIInstrInfo.cpp | 18 | ||||
-rw-r--r-- | lib/Target/AMDGPU/SIInstrInfo.h | 8 | ||||
-rw-r--r-- | test/CodeGen/MIR/AMDGPU/target-flags.mir | 29 |
3 files changed, 55 insertions, 0 deletions
diff --git a/lib/Target/AMDGPU/SIInstrInfo.cpp b/lib/Target/AMDGPU/SIInstrInfo.cpp index b6784ec14e9..5a9089deb7a 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -4320,6 +4320,24 @@ SIInstrInfo::CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const return new GCNHazardRecognizer(MF); } +std::pair<unsigned, unsigned> +SIInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const { + return std::make_pair(TF & MO_MASK, TF & ~MO_MASK); +} + +ArrayRef<std::pair<unsigned, const char *>> +SIInstrInfo::getSerializableDirectMachineOperandTargetFlags() const { + static const std::pair<unsigned, const char *> TargetFlags[] = { + { MO_GOTPCREL, "amdgpu-gotprel" }, + { MO_GOTPCREL32_LO, "amdgpu-gotprel32-lo" }, + { MO_GOTPCREL32_HI, "amdgpu-gotprel32-hi" }, + { MO_REL32_LO, "amdgpu-rel32-lo" }, + { MO_REL32_HI, "amdgpu-rel32-hi" } + }; + + return makeArrayRef(TargetFlags); +} + bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI) const { return !MI.isTerminator() && MI.getOpcode() != AMDGPU::COPY && MI.modifiesRegister(AMDGPU::EXEC, &RI); diff --git a/lib/Target/AMDGPU/SIInstrInfo.h b/lib/Target/AMDGPU/SIInstrInfo.h index 74b48c76180..d00c0d4a7f4 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.h +++ b/lib/Target/AMDGPU/SIInstrInfo.h @@ -100,6 +100,8 @@ protected: public: enum TargetOperandFlags { + MO_MASK = 0x7, + MO_NONE = 0, // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL. MO_GOTPCREL = 1, @@ -781,9 +783,15 @@ public: void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const; + std::pair<unsigned, unsigned> + decomposeMachineOperandsTargetFlags(unsigned TF) const override; + ArrayRef<std::pair<int, const char *>> getSerializableTargetIndices() const override; + ArrayRef<std::pair<unsigned, const char *>> + getSerializableDirectMachineOperandTargetFlags() const override; + ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override; diff --git a/test/CodeGen/MIR/AMDGPU/target-flags.mir b/test/CodeGen/MIR/AMDGPU/target-flags.mir new file mode 100644 index 00000000000..7d288dd1b04 --- /dev/null +++ b/test/CodeGen/MIR/AMDGPU/target-flags.mir @@ -0,0 +1,29 @@ +# RUN: llc -march=amdgcn -run-pass none -o - %s | FileCheck %s +--- | + define amdgpu_kernel void @flags() { + ret void + } + + declare void @foo() +... +--- + +# CHECK: SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc +# CHECK: %1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo + +name: flags +liveins: + - { reg: '%sgpr0_sgpr1' } +frameInfo: + maxAlignment: 8 +registers: + - { id: 0, class: sreg_64, preferred-register: '' } + - { id: 1, class: sreg_64, preferred-register: '' } +body: | + bb.0: + liveins: %sgpr0_sgpr1 + %0 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc + %1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo + + S_ENDPGM +... |