diff options
author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-12-13 10:30:45 +0000 |
---|---|---|
committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-12-13 10:30:45 +0000 |
commit | c84690975acd7c5f43e4c44d4653a9f7e384ba8f (patch) | |
tree | f0535db11a70ddf14bd51ac62383f4a4557e578e | |
parent | 061f5ff24a3062e2793bcb38adec31d4326aa689 (diff) |
[CodeGen] Print constant pool index operands as %const.0 + 8 in both MIR and debug output
Work towards the unification of MIR and debug output by printing
`%const.0 + 8` instead of `<cp#0+8>` and `%const.0 - 8` instead of
`<cp#0-8>`.
Only debug syntax is affected.
Differential Revision: https://reviews.llvm.org/D41116
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320564 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | docs/MIRLangRef.rst | 49 | ||||
-rw-r--r-- | lib/CodeGen/MIRPrinter.cpp | 7 | ||||
-rw-r--r-- | lib/CodeGen/MachineOperand.cpp | 16 | ||||
-rw-r--r-- | test/CodeGen/ARM/subreg-remat.ll | 4 | ||||
-rw-r--r-- | test/CodeGen/X86/2010-05-12-FastAllocKills.ll | 4 | ||||
-rw-r--r-- | unittests/CodeGen/MachineOperandTest.cpp | 32 |
6 files changed, 97 insertions, 15 deletions
diff --git a/docs/MIRLangRef.rst b/docs/MIRLangRef.rst index 7615a28112d..82a61bcde86 100644 --- a/docs/MIRLangRef.rst +++ b/docs/MIRLangRef.rst @@ -549,6 +549,53 @@ lower bits from the 32-bit virtual register 0 to the 8-bit virtual register 1: The names of the subregister indices are target specific, and are typically defined in the target's ``*RegisterInfo.td`` file. +Constant Pool Indices +^^^^^^^^^^^^^^^^^^^^^ + +A constant pool index (CPI) operand is printed using its index in the +function's ``MachineConstantPool`` and an offset. + +For example, a CPI with the index 1 and offset 8: + +.. code-block:: text + + %1:gr64 = MOV64ri %const.1 + 8 + +For a CPI with the index 0 and offset -12: + +.. code-block:: text + + %1:gr64 = MOV64ri %const.0 - 12 + +A constant pool entry is bound to a LLVM IR ``Constant`` or a target-specific +``MachineConstantPoolValue``. When serializing all the function's constants the +following format is used: + +.. code-block:: text + + constants: + - id: <index> + value: <value> + alignment: <alignment> + isTargetSpecific: <target-specific> + +where ``<index>`` is a 32-bit unsigned integer, ``<value>`` is a `LLVM IR Constant +<https://www.llvm.org/docs/LangRef.html#constants>`_, alignment is a 32-bit +unsigned integer, and ``<target-specific>`` is either true or false. + +Example: + +.. code-block:: text + + constants: + - id: 0 + value: 'double 3.250000e+00' + alignment: 8 + - id: 1 + value: 'g-(LPC0+8)' + alignment: 4 + isTargetSpecific: true + Global Value Operands ^^^^^^^^^^^^^^^^^^^^^ @@ -578,8 +625,6 @@ the '@' prefix, like in the following examples: ``@0``, ``@989``. .. TODO: Describe the frame information YAML mapping. .. TODO: Describe the syntax of the stack object machine operands and their YAML definitions. -.. TODO: Describe the syntax of the constant pool machine operands and their - YAML definitions. .. TODO: Describe the syntax of the jump table machine operands and their YAML definitions. .. TODO: Describe the syntax of the block address machine operands. diff --git a/lib/CodeGen/MIRPrinter.cpp b/lib/CodeGen/MIRPrinter.cpp index ccec5b4348d..f4f248e6053 100644 --- a/lib/CodeGen/MIRPrinter.cpp +++ b/lib/CodeGen/MIRPrinter.cpp @@ -862,7 +862,8 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx, LLVM_FALLTHROUGH; case MachineOperand::MO_Register: case MachineOperand::MO_CImmediate: - case MachineOperand::MO_MachineBasicBlock: { + case MachineOperand::MO_MachineBasicBlock: + case MachineOperand::MO_ConstantPoolIndex: { unsigned TiedOperandIdx = 0; if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef()) TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx); @@ -877,10 +878,6 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx, case MachineOperand::MO_FrameIndex: printStackObjectReference(Op.getIndex()); break; - case MachineOperand::MO_ConstantPoolIndex: - OS << "%const." << Op.getIndex(); - printOffset(Op.getOffset()); - break; case MachineOperand::MO_TargetIndex: OS << "target-index("; if (const auto *Name = diff --git a/lib/CodeGen/MachineOperand.cpp b/lib/CodeGen/MachineOperand.cpp index b618e605dca..2a2f8f29c48 100644 --- a/lib/CodeGen/MachineOperand.cpp +++ b/lib/CodeGen/MachineOperand.cpp @@ -376,6 +376,16 @@ static void tryToGetTargetInfo(const MachineOperand &MO, } } +static void printOffset(raw_ostream &OS, int64_t Offset) { + if (Offset == 0) + return; + if (Offset < 0) { + OS << " - " << -Offset; + return; + } + OS << " + " << Offset; +} + void MachineOperand::printSubregIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI) { OS << "%subreg."; @@ -486,10 +496,8 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST, OS << "<fi#" << getIndex() << '>'; break; case MachineOperand::MO_ConstantPoolIndex: - OS << "<cp#" << getIndex(); - if (getOffset()) - OS << "+" << getOffset(); - OS << '>'; + OS << "%const." << getIndex(); + printOffset(OS, getOffset()); break; case MachineOperand::MO_TargetIndex: OS << "<ti#" << getIndex(); diff --git a/test/CodeGen/ARM/subreg-remat.ll b/test/CodeGen/ARM/subreg-remat.ll index 64d79413413..8d0d09fe120 100644 --- a/test/CodeGen/ARM/subreg-remat.ll +++ b/test/CodeGen/ARM/subreg-remat.ll @@ -5,7 +5,7 @@ target triple = "thumbv7-apple-ios" ; The vector %v2 is built like this: ; ; %6:ssub_1 = ... -; %6:ssub_0 = VLDRS <cp#0>, 0, pred:14, pred:%noreg; mem:LD4[ConstantPool] DPR_VFP2:%6 +; %6:ssub_0 = VLDRS %const.0, 0, pred:14, pred:%noreg; mem:LD4[ConstantPool] DPR_VFP2:%6 ; ; When %6 spills, the VLDRS constant pool load cannot be rematerialized ; since it implicitly reads the ssub_1 sub-register. @@ -31,7 +31,7 @@ define void @f1(float %x, <2 x float>* %p) { ; because the bits are undef, we should rematerialize. The vector is now built ; like this: ; -; %2:ssub_0 = VLDRS <cp#0>, 0, pred:14, pred:%noreg, implicit-def %2; mem:LD4[ConstantPool] +; %2:ssub_0 = VLDRS %const.0, 0, pred:14, pred:%noreg, implicit-def %2; mem:LD4[ConstantPool] ; ; The extra <imp-def> operand indicates that the instruction fully defines the ; virtual register. It doesn't read the old value. diff --git a/test/CodeGen/X86/2010-05-12-FastAllocKills.ll b/test/CodeGen/X86/2010-05-12-FastAllocKills.ll index 39031806a9a..0d6609ea823 100644 --- a/test/CodeGen/X86/2010-05-12-FastAllocKills.ll +++ b/test/CodeGen/X86/2010-05-12-FastAllocKills.ll @@ -6,7 +6,7 @@ target triple = "x86_64-apple-darwin" ;%bb.5: derived from LLVM BB %bb10 ; Predecessors according to CFG: %bb.4 %bb.5 ; %reg1024 = MOV_Fp8080 %reg1034 -; %reg1025 = MUL_Fp80m32 %reg1024, %rip, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool] +; %reg1025 = MUL_Fp80m32 %reg1024, %rip, 1, %reg0, %const.0, %reg0; mem:LD4[ConstantPool] ; %reg1034 = MOV_Fp8080 %reg1025 ; FP_REG_KILL implicit-def %fp0, implicit-def %fp1, implicit-def %fp2, implicit-def %fp3, implicit-def %fp4, implicit-def %fp5, implicit-def %fp6 ; JMP_4 <%bb.5> @@ -17,7 +17,7 @@ target triple = "x86_64-apple-darwin" ; Predecessors according to CFG: %bb.4 %bb.5 ; %fp0 = LD_Fp80m <fi#3>, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4) ; %fp1 = MOV_Fp8080 killed %fp0 -; %fp2 = MUL_Fp80m32 %fp1, %rip, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool] +; %fp2 = MUL_Fp80m32 %fp1, %rip, 1, %reg0, %const.0, %reg0; mem:LD4[ConstantPool] ; %fp0 = MOV_Fp8080 %fp2 ; ST_FpP80m <fi#3>, 1, %reg0, 0, %reg0, killed %fp0; mem:ST10[FixedStack3](align=4) ; ST_FpP80m <fi#4>, 1, %reg0, 0, %reg0, killed %fp1; mem:ST10[FixedStack4](align=4) diff --git a/unittests/CodeGen/MachineOperandTest.cpp b/unittests/CodeGen/MachineOperandTest.cpp index 24a7f5563ff..c21bff60db0 100644 --- a/unittests/CodeGen/MachineOperandTest.cpp +++ b/unittests/CodeGen/MachineOperandTest.cpp @@ -119,4 +119,36 @@ TEST(MachineOperandTest, PrintSubRegIndex) { ASSERT_TRUE(OS.str() == "%subreg.3"); } +TEST(MachineOperandTest, PrintCPI) { + // Create a MachineOperand with a constant pool index and print it. + MachineOperand MO = MachineOperand::CreateCPI(0, 8); + + // Checking some preconditions on the newly created + // MachineOperand. + ASSERT_TRUE(MO.isCPI()); + ASSERT_TRUE(MO.getIndex() == 0); + ASSERT_TRUE(MO.getOffset() == 8); + + // Print a MachineOperand containing a constant pool index and a positive + // offset. + std::string str; + { + raw_string_ostream OS(str); + MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr); + ASSERT_TRUE(OS.str() == "%const.0 + 8"); + } + + str.clear(); + + MO.setOffset(-12); + + // Print a MachineOperand containing a constant pool index and a negative + // offset. + { + raw_string_ostream OS(str); + MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr); + ASSERT_TRUE(OS.str() == "%const.0 - 12"); + } +} + } // end namespace |