diff options
author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-12-11 14:35:48 +0000 |
---|---|---|
committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-12-11 14:35:48 +0000 |
commit | 6c0ae87241fcdd95aacfd89d70216fb3fb9aba07 (patch) | |
tree | 1af8f627e653e74869d522c0df257809be372c76 | |
parent | 3386088d3ed65b1d5a446bce6eab00d6dbebffc8 (diff) |
[PowerPC] Sign-extend negative constant stores
Second part of https://reviews.llvm.org/D40348.
Revision r318436 has extended all constants feeding a store to 64 bits
to allow for CSE on the SDAG. However, negative constants were zero extended
which made the constant being loaded appear to be a positive value larger than
16 bits. This resulted in long sequences to materialize such constants
rather than simply a "load immediate". This patch just sign-extends those
updated constants so that they remain 16-bit signed immediates if they started
out that way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320368 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 8 | ||||
-rw-r--r-- | test/CodeGen/PowerPC/testComparesigeui.ll | 6 | ||||
-rw-r--r-- | test/CodeGen/PowerPC/testComparesllgeui.ll | 6 |
3 files changed, 10 insertions, 10 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 3fe9fe73499..af2ea695089 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -12228,8 +12228,12 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, EVT VT = N->getOperand(1).getValueType(); if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() && isa<ConstantSDNode>(N->getOperand(1)) && VT == MVT::i32) { - SDValue Const64 = DAG.getConstant(N->getConstantOperandVal(1), dl, - MVT::i64); + // Need to sign-extended to 64-bits to handle negative values. + EVT MemVT = cast<StoreSDNode>(N)->getMemoryVT(); + uint64_t Val64 = SignExtend64(N->getConstantOperandVal(1), + MemVT.getSizeInBits()); + SDValue Const64 = DAG.getConstant(Val64, dl, MVT::i64); + // DAG.getTruncStore() can't be used here because it doesn't accept // the general (base + offset) addressing mode. // So we use UpdateNodeOperands and setTruncatingStore instead. diff --git a/test/CodeGen/PowerPC/testComparesigeui.ll b/test/CodeGen/PowerPC/testComparesigeui.ll index a77cea72cfa..ac55500432f 100644 --- a/test/CodeGen/PowerPC/testComparesigeui.ll +++ b/test/CodeGen/PowerPC/testComparesigeui.ll @@ -105,10 +105,8 @@ entry: store i32 %conv1, i32* @glob ret void ; CHECK-LABEL: @test_igeui_sext_z_store -; CHECK: li [[REG1:r[0-9]+]], 0 -; CHECK: oris [[REG2:r[0-9]+]], [[REG1]], 65535 -; CHECK: ori [[REG3:r[0-9]+]], [[REG2]], 65535 -; CHECK: stw [[REG3]] +; CHECK: li [[REG1:r[0-9]+]], -1 +; CHECK: stw [[REG1]] ; CHECK: blr } diff --git a/test/CodeGen/PowerPC/testComparesllgeui.ll b/test/CodeGen/PowerPC/testComparesllgeui.ll index 856d3a0f3cc..9e971b140de 100644 --- a/test/CodeGen/PowerPC/testComparesllgeui.ll +++ b/test/CodeGen/PowerPC/testComparesllgeui.ll @@ -105,10 +105,8 @@ entry: store i32 %sub, i32* @glob ret void ; CHECK-LABEL: @test_llgeui_sext_z_store -; CHECK: li [[REG1:r[0-9]+]], 0 -; CHECK: oris [[REG2:r[0-9]+]], [[REG1]], 65535 -; CHECK: ori [[REG3:r[0-9]+]], [[REG2]], 65535 -; CHECK: stw [[REG3]] +; CHECK: li [[REG1:r[0-9]+]], -1 +; CHECK: stw [[REG1]] ; CHECK: blr } |