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authorCraig Topper <craig.topper@intel.com>2017-12-13 07:26:17 +0000
committerCraig Topper <craig.topper@intel.com>2017-12-13 07:26:17 +0000
commit56d08f7e75230989a37c3464cb4d8fbd8d830d77 (patch)
treeeb107d503838010ebdfc8485d6cde5049cc680a7
parent596e2d5bc42cabee23ad7e64160b4a0dc4e7a3dc (diff)
[Targets] Don't automatically include the scheduler class enum from *GenInstrInfo.inc with GET_INSTRINFO_ENUM. Make targets request is separately.
Most of the targets don't need the scheduler class enum. I have an X86 scheduler model change that causes some names in the enum to become about 18000 characters long. This is because using instregex in scheduler models causes the scheduler class to get named with every instruction that matches the regex concatenated together. MSVC has a limit of 4096 characters for an identifier name. Rather than trying to come up with way to reduce the name length, I'm just going to sidestep the problem by not including the enum in X86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320552 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h2
-rw-r--r--lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h1
-rw-r--r--lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h1
-rw-r--r--utils/TableGen/InstrInfoEmitter.cpp10
4 files changed, 13 insertions, 1 deletions
diff --git a/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h b/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
index 56bcff48717..0b3563303ad 100644
--- a/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
+++ b/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
@@ -60,7 +60,9 @@ createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI,
#define GET_INSTRINFO_ENUM
#define GET_INSTRINFO_OPERAND_ENUM
+#define GET_INSTRINFO_SCHED_ENUM
#include "AMDGPUGenInstrInfo.inc"
+#undef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_ENUM
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
index e53208fffee..05d17c368dc 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
@@ -82,6 +82,7 @@ unsigned HexagonGetLastSlot();
// Defines symbolic names for the Hexagon instructions.
//
#define GET_INSTRINFO_ENUM
+#define GET_INSTRINFO_SCHED_ENUM
#include "HexagonGenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h b/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
index 99fec6c554b..80a74c09a59 100644
--- a/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
+++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
@@ -101,6 +101,7 @@ static inline bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
// Defines symbolic names for the PowerPC instructions.
//
#define GET_INSTRINFO_ENUM
+#define GET_INSTRINFO_SCHED_ENUM
#include "PPCGenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index e270a17356f..379e3245d06 100644
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -588,6 +588,14 @@ void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
OS << " " << Inst->TheDef->getName() << "\t= " << Num++ << ",\n";
OS << " INSTRUCTION_LIST_END = " << Num << "\n";
OS << " };\n\n";
+ OS << "} // end " << Namespace << " namespace\n";
+ OS << "} // end llvm namespace\n";
+ OS << "#endif // GET_INSTRINFO_ENUM\n\n";
+
+ OS << "#ifdef GET_INSTRINFO_SCHED_ENUM\n";
+ OS << "#undef GET_INSTRINFO_SCHED_ENUM\n";
+ OS << "namespace llvm {\n\n";
+ OS << "namespace " << Namespace << " {\n";
OS << "namespace Sched {\n";
OS << " enum {\n";
Num = 0;
@@ -599,7 +607,7 @@ void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
OS << "} // end " << Namespace << " namespace\n";
OS << "} // end llvm namespace\n";
- OS << "#endif // GET_INSTRINFO_ENUM\n\n";
+ OS << "#endif // GET_INSTRINFO_SCHED_ENUM\n\n";
}
namespace llvm {