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| author | Simon Dardis <simon.dardis@mips.com> | 2018-02-23 10:19:00 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@mips.com> | 2018-02-23 10:19:00 +0000 |
| commit | 4cc9e1df327ea8ed5f7659e48f0f787f5dd21518 (patch) | |
| tree | e7df7a59ddaaf6bf9b80cb2869c84cd3ada3b9ea | |
| parent | 78c90d9dcc9ae4b7cafb37148d311fbf193bec2d (diff) | |
[mips] 6.0 Release notes
Reviewers: atanasyan, arichardson, petarj, smaksimovic, abeserminji
Differential Revision: https://reviews.llvm.org/D43573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@325876 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | docs/ReleaseNotes.rst | 40 |
1 files changed, 38 insertions, 2 deletions
diff --git a/docs/ReleaseNotes.rst b/docs/ReleaseNotes.rst index a2e5832c0ec..91e7dbb1adf 100644 --- a/docs/ReleaseNotes.rst +++ b/docs/ReleaseNotes.rst @@ -113,8 +113,44 @@ Changes to the Hexagon Target Changes to the MIPS Target -------------------------- - During this release ... - +Fixed numerous bugs: + +* fpowi on MIPS64 giving incorrect results when used with a negative integer. +* Usage of the asm 'c' constraint with the wrong datatype causing an + assert/crash. +* Fixed a conversion bug when using the DSP ASE. +* Fixed an inconsistency where objects were not marked as using the microMIPS as + when the micromips function attribute or the ".set micromips" directive was + used. +* Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot + filler, fixing a class of rare edge case bugs where the delay slot filler + would violate ISA restrictions. +* Fixed a crash when using a type of unknown size with gp relative addressing. +* Corrected the j macro for microMIPS. +* Corrected the encoding of movep for microMIPS32r6. +* Fixed an issue with the usage of insert instructions having an invalid set of + operands. +* Fixed an issue where TLS symbols where not marked as such. +* Enabled the usage of register scavanging with MSA, due to its' shorter offsets + for loads and stores. +* Corrected the ELF headers when using the DSP ASE. + +New features: + +* The long branch pass now generates some R6 specific instructions when + targeting MIPSR6. +* The delay slot filler now performs more branch conversions if delay slots + cannot be filled. +* The MIPS MT ASE is now fully supported. +* Added support for the ``lapc`` pseudo instruction. +* Improved the selection of multiple instructions (``dext``, ``nmadd``, + ``nmsub``). +* Further improved microMIPS codesize reduction. + +Deprecation notices: + +* microMIPS64R6 support was been deprecated since 5.0, and has now been + completely removed. Changes to the PowerPC Target ----------------------------- |