diff options
author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-12-19 21:47:10 +0000 |
---|---|---|
committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-12-19 21:47:10 +0000 |
commit | 234b36e423440483bd70348d31942936dd0f9ef7 (patch) | |
tree | 631fd3054860776e79c70aab6364b536e559c211 | |
parent | 43c2ba74fca95ca61abf3717b10a8a3b7369f3b3 (diff) |
[CodeGen] Move printing MO_IntrinsicID operands to MachineOperand::print
Work towards the unification of MIR and debug output by refactoring the
interfaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321112 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | docs/MIRLangRef.rst | 12 | ||||
-rw-r--r-- | lib/CodeGen/MIRPrinter.cpp | 9 | ||||
-rw-r--r-- | lib/CodeGen/MachineOperand.cpp | 4 | ||||
-rw-r--r-- | unittests/CodeGen/MachineOperandTest.cpp | 17 |
4 files changed, 33 insertions, 9 deletions
diff --git a/docs/MIRLangRef.rst b/docs/MIRLangRef.rst index 150e4e21375..1176435c876 100644 --- a/docs/MIRLangRef.rst +++ b/docs/MIRLangRef.rst @@ -724,6 +724,18 @@ The syntax for the ``returnaddress`` intrinsic is: %x0 = COPY intrinsic(@llvm.returnaddress) +Predicate Operands +^^^^^^^^^^^^^^^^^^ + +A Predicate operand contains an IR predicate from ``CmpInst::Predicate``, like +``ICMP_EQ``, etc. + +For an int eq predicate ``ICMP_EQ``, the syntax is: + +.. code-block:: text + + %2:gpr(s32) = G_ICMP intpred(eq), %0, %1 + .. TODO: Describe the parsers default behaviour when optional YAML attributes are missing. .. TODO: Describe the syntax for the bundled instructions. diff --git a/lib/CodeGen/MIRPrinter.cpp b/lib/CodeGen/MIRPrinter.cpp index 9b38b893973..6b9da344166 100644 --- a/lib/CodeGen/MIRPrinter.cpp +++ b/lib/CodeGen/MIRPrinter.cpp @@ -785,7 +785,8 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx, case MachineOperand::MO_Metadata: case MachineOperand::MO_MCSymbol: case MachineOperand::MO_CFIIndex: - case MachineOperand::MO_IntrinsicID: { + case MachineOperand::MO_IntrinsicID: + case MachineOperand::MO_Predicate: { unsigned TiedOperandIdx = 0; if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef()) TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx); @@ -814,12 +815,6 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx, printCustomRegMask(Op.getRegMask(), OS, TRI); break; } - case MachineOperand::MO_Predicate: { - auto Pred = static_cast<CmpInst::Predicate>(Op.getPredicate()); - OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred(" - << CmpInst::getPredicateName(Pred) << ')'; - break; - } } } diff --git a/lib/CodeGen/MachineOperand.cpp b/lib/CodeGen/MachineOperand.cpp index 586e826be58..fee99c91bbe 100644 --- a/lib/CodeGen/MachineOperand.cpp +++ b/lib/CodeGen/MachineOperand.cpp @@ -807,8 +807,8 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST, } case MachineOperand::MO_Predicate: { auto Pred = static_cast<CmpInst::Predicate>(getPredicate()); - OS << '<' << (CmpInst::isIntPredicate(Pred) ? "intpred" : "floatpred") - << CmpInst::getPredicateName(Pred) << '>'; + OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred(" + << CmpInst::getPredicateName(Pred) << ')'; break; } } diff --git a/unittests/CodeGen/MachineOperandTest.cpp b/unittests/CodeGen/MachineOperandTest.cpp index cce85cafb2a..78a20b83648 100644 --- a/unittests/CodeGen/MachineOperandTest.cpp +++ b/unittests/CodeGen/MachineOperandTest.cpp @@ -10,6 +10,7 @@ #include "llvm/CodeGen/MachineOperand.h" #include "llvm/ADT/ilist_node.h" #include "llvm/IR/Constants.h" +#include "llvm/IR/InstrTypes.h" #include "llvm/IR/LLVMContext.h" #include "llvm/IR/Module.h" #include "llvm/IR/ModuleSlotTracker.h" @@ -382,4 +383,20 @@ TEST(MachineOperandTest, PrintIntrinsicID) { } } +TEST(MachineOperandTest, PrintPredicate) { + // Create a MachineOperand with a generic intrinsic ID. + MachineOperand MO = MachineOperand::CreatePredicate(CmpInst::ICMP_EQ); + + // Checking some preconditions on the newly created + // MachineOperand. + ASSERT_TRUE(MO.isPredicate()); + ASSERT_TRUE(MO.getPredicate() == CmpInst::ICMP_EQ); + + std::string str; + // Print a MachineOperand containing a int predicate ICMP_EQ. + raw_string_ostream OS(str); + MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr); + ASSERT_TRUE(OS.str() == "intpred(eq)"); +} + } // end namespace |