diff options
author | Tom Stellard <tstellar@redhat.com> | 2018-04-11 23:04:06 +0000 |
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committer | Tom Stellard <tstellar@redhat.com> | 2018-04-11 23:04:06 +0000 |
commit | e73bd18593c1c246e1078a65711b5ba2a733c6b5 (patch) | |
tree | ff43dcf18a308173cc8a575265ac2201c01d0d62 | |
parent | 44e5d1278bb04bec281a921b0c63a8d22e1731f6 (diff) |
Merging r329359 and r329363:
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r329359 | manojgupta | 2018-04-05 15:47:25 -0700 (Thu, 05 Apr 2018) | 11 lines
Attempt to fix Mips breakages.
Summary:
Replace ArrayRefs by actual std::array objects so that there are
no dangling references.
Reviewers: rsmith, gkistanova
Subscribers: sdardis, arichardson, llvm-commits
Differential Revision: https://reviews.llvm.org/D45338
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r329363 | manojgupta | 2018-04-05 16:23:29 -0700 (Thu, 05 Apr 2018) | 5 lines
Fix lld-x86_64-darwin13 build fails.
Use double braces in std::array initialization
to keep Darwin builders happy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@329859 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/Mips/MipsFastISel.cpp | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/lib/Target/Mips/MipsFastISel.cpp b/lib/Target/Mips/MipsFastISel.cpp index 8bbac3ed7cf..d3048c7390e 100644 --- a/lib/Target/Mips/MipsFastISel.cpp +++ b/lib/Target/Mips/MipsFastISel.cpp @@ -67,6 +67,7 @@ #include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" #include <algorithm> +#include <array> #include <cassert> #include <cstdint> @@ -1306,13 +1307,13 @@ bool MipsFastISel::fastLowerArguments() { return false; } - const ArrayRef<MCPhysReg> GPR32ArgRegs = {Mips::A0, Mips::A1, Mips::A2, - Mips::A3}; - const ArrayRef<MCPhysReg> FGR32ArgRegs = {Mips::F12, Mips::F14}; - const ArrayRef<MCPhysReg> AFGR64ArgRegs = {Mips::D6, Mips::D7}; - ArrayRef<MCPhysReg>::iterator NextGPR32 = GPR32ArgRegs.begin(); - ArrayRef<MCPhysReg>::iterator NextFGR32 = FGR32ArgRegs.begin(); - ArrayRef<MCPhysReg>::iterator NextAFGR64 = AFGR64ArgRegs.begin(); + std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2, + Mips::A3}}; + std::array<MCPhysReg, 2> FGR32ArgRegs = {{Mips::F12, Mips::F14}}; + std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}}; + auto NextGPR32 = GPR32ArgRegs.begin(); + auto NextFGR32 = FGR32ArgRegs.begin(); + auto NextAFGR64 = AFGR64ArgRegs.begin(); struct AllocatedReg { const TargetRegisterClass *RC; |