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-rw-r--r--include/dt-bindings/clock/exynos4.h35
-rw-r--r--include/dt-bindings/clock/gxbb-clkc.h11
-rw-r--r--include/dt-bindings/clock/imx7d-clock.h8
-rw-r--r--include/dt-bindings/clock/mt2712-clk.h427
-rw-r--r--include/dt-bindings/clock/mt7622-clk.h289
-rw-r--r--include/dt-bindings/clock/qcom,rpmcc.h17
-rw-r--r--include/dt-bindings/clock/r8a77970-cpg-mssr.h48
-rw-r--r--include/dt-bindings/clock/s3c2443.h2
-rw-r--r--include/dt-bindings/clock/sun4i-a10-ccu.h2
-rw-r--r--include/dt-bindings/clock/sun6i-a31-ccu.h4
-rw-r--r--include/linux/clk-provider.h25
-rw-r--r--include/linux/soc/qcom/smd-rpm.h4
-rw-r--r--include/soc/at91/atmel-sfr.h2
13 files changed, 864 insertions, 10 deletions
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index c40111f36d5e..e9f9d400c322 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -272,4 +272,39 @@
/* must be greater than maximal clock id */
#define CLK_NR_CLKS 461
+/* Exynos4x12 ISP clocks */
+#define CLK_ISP_FIMC_ISP 1
+#define CLK_ISP_FIMC_DRC 2
+#define CLK_ISP_FIMC_FD 3
+#define CLK_ISP_FIMC_LITE0 4
+#define CLK_ISP_FIMC_LITE1 5
+#define CLK_ISP_MCUISP 6
+#define CLK_ISP_GICISP 7
+#define CLK_ISP_SMMU_ISP 8
+#define CLK_ISP_SMMU_DRC 9
+#define CLK_ISP_SMMU_FD 10
+#define CLK_ISP_SMMU_LITE0 11
+#define CLK_ISP_SMMU_LITE1 12
+#define CLK_ISP_PPMUISPMX 13
+#define CLK_ISP_PPMUISPX 14
+#define CLK_ISP_MCUCTL_ISP 15
+#define CLK_ISP_MPWM_ISP 16
+#define CLK_ISP_I2C0_ISP 17
+#define CLK_ISP_I2C1_ISP 18
+#define CLK_ISP_MTCADC_ISP 19
+#define CLK_ISP_PWM_ISP 20
+#define CLK_ISP_WDT_ISP 21
+#define CLK_ISP_UART_ISP 22
+#define CLK_ISP_ASYNCAXIM 23
+#define CLK_ISP_SMMU_ISPCX 24
+#define CLK_ISP_SPI0_ISP 25
+#define CLK_ISP_SPI1_ISP 26
+
+#define CLK_ISP_DIV_ISP0 27
+#define CLK_ISP_DIV_ISP1 28
+#define CLK_ISP_DIV_MCUISP0 29
+#define CLK_ISP_DIV_MCUISP1 30
+
+#define CLK_NR_ISP_CLKS 31
+
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 8c92528aa48a..8ba99a5e3fd3 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -114,5 +114,16 @@
#define CLKID_SD_EMMC_A_CLK0 119
#define CLKID_SD_EMMC_B_CLK0 122
#define CLKID_SD_EMMC_C_CLK0 125
+#define CLKID_VPU_0_SEL 126
+#define CLKID_VPU_0 128
+#define CLKID_VPU_1_SEL 129
+#define CLKID_VPU_1 131
+#define CLKID_VPU 132
+#define CLKID_VAPB_0_SEL 133
+#define CLKID_VAPB_0 135
+#define CLKID_VAPB_1_SEL 136
+#define CLKID_VAPB_1 138
+#define CLKID_VAPB_SEL 139
+#define CLKID_VAPB 140
#endif /* __GXBB_CLKC_H */
diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
index de62a83b6c80..e2f99ae72d5c 100644
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -80,10 +80,10 @@
#define IMX7D_ARM_M4_ROOT_SRC 67
#define IMX7D_ARM_M4_ROOT_CG 68
#define IMX7D_ARM_M4_ROOT_DIV 69
-#define IMX7D_ARM_M0_ROOT_CLK 70
-#define IMX7D_ARM_M0_ROOT_SRC 71
-#define IMX7D_ARM_M0_ROOT_CG 72
-#define IMX7D_ARM_M0_ROOT_DIV 73
+#define IMX7D_ARM_M0_ROOT_CLK 70 /* unused */
+#define IMX7D_ARM_M0_ROOT_SRC 71 /* unused */
+#define IMX7D_ARM_M0_ROOT_CG 72 /* unused */
+#define IMX7D_ARM_M0_ROOT_DIV 73 /* unused */
#define IMX7D_MAIN_AXI_ROOT_CLK 74
#define IMX7D_MAIN_AXI_ROOT_SRC 75
#define IMX7D_MAIN_AXI_ROOT_CG 76
diff --git a/include/dt-bindings/clock/mt2712-clk.h b/include/dt-bindings/clock/mt2712-clk.h
new file mode 100644
index 000000000000..48a8e797a617
--- /dev/null
+++ b/include/dt-bindings/clock/mt2712-clk.h
@@ -0,0 +1,427 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT2712_H
+#define _DT_BINDINGS_CLK_MT2712_H
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_MAINPLL 0
+#define CLK_APMIXED_UNIVPLL 1
+#define CLK_APMIXED_VCODECPLL 2
+#define CLK_APMIXED_VENCPLL 3
+#define CLK_APMIXED_APLL1 4
+#define CLK_APMIXED_APLL2 5
+#define CLK_APMIXED_LVDSPLL 6
+#define CLK_APMIXED_LVDSPLL2 7
+#define CLK_APMIXED_MSDCPLL 8
+#define CLK_APMIXED_MSDCPLL2 9
+#define CLK_APMIXED_TVDPLL 10
+#define CLK_APMIXED_MMPLL 11
+#define CLK_APMIXED_ARMCA35PLL 12
+#define CLK_APMIXED_ARMCA72PLL 13
+#define CLK_APMIXED_ETHERPLL 14
+#define CLK_APMIXED_NR_CLK 15
+
+/* TOPCKGEN */
+
+#define CLK_TOP_ARMCA35PLL 0
+#define CLK_TOP_ARMCA35PLL_600M 1
+#define CLK_TOP_ARMCA35PLL_400M 2
+#define CLK_TOP_ARMCA72PLL 3
+#define CLK_TOP_SYSPLL 4
+#define CLK_TOP_SYSPLL_D2 5
+#define CLK_TOP_SYSPLL1_D2 6
+#define CLK_TOP_SYSPLL1_D4 7
+#define CLK_TOP_SYSPLL1_D8 8
+#define CLK_TOP_SYSPLL1_D16 9
+#define CLK_TOP_SYSPLL_D3 10
+#define CLK_TOP_SYSPLL2_D2 11
+#define CLK_TOP_SYSPLL2_D4 12
+#define CLK_TOP_SYSPLL_D5 13
+#define CLK_TOP_SYSPLL3_D2 14
+#define CLK_TOP_SYSPLL3_D4 15
+#define CLK_TOP_SYSPLL_D7 16
+#define CLK_TOP_SYSPLL4_D2 17
+#define CLK_TOP_SYSPLL4_D4 18
+#define CLK_TOP_UNIVPLL 19
+#define CLK_TOP_UNIVPLL_D7 20
+#define CLK_TOP_UNIVPLL_D26 21
+#define CLK_TOP_UNIVPLL_D52 22
+#define CLK_TOP_UNIVPLL_D104 23
+#define CLK_TOP_UNIVPLL_D208 24
+#define CLK_TOP_UNIVPLL_D2 25
+#define CLK_TOP_UNIVPLL1_D2 26
+#define CLK_TOP_UNIVPLL1_D4 27
+#define CLK_TOP_UNIVPLL1_D8 28
+#define CLK_TOP_UNIVPLL_D3 29
+#define CLK_TOP_UNIVPLL2_D2 30
+#define CLK_TOP_UNIVPLL2_D4 31
+#define CLK_TOP_UNIVPLL2_D8 32
+#define CLK_TOP_UNIVPLL_D5 33
+#define CLK_TOP_UNIVPLL3_D2 34
+#define CLK_TOP_UNIVPLL3_D4 35
+#define CLK_TOP_UNIVPLL3_D8 36
+#define CLK_TOP_F_MP0_PLL1 37
+#define CLK_TOP_F_MP0_PLL2 38
+#define CLK_TOP_F_BIG_PLL1 39
+#define CLK_TOP_F_BIG_PLL2 40
+#define CLK_TOP_F_BUS_PLL1 41
+#define CLK_TOP_F_BUS_PLL2 42
+#define CLK_TOP_APLL1 43
+#define CLK_TOP_APLL1_D2 44
+#define CLK_TOP_APLL1_D4 45
+#define CLK_TOP_APLL1_D8 46
+#define CLK_TOP_APLL1_D16 47
+#define CLK_TOP_APLL2 48
+#define CLK_TOP_APLL2_D2 49
+#define CLK_TOP_APLL2_D4 50
+#define CLK_TOP_APLL2_D8 51
+#define CLK_TOP_APLL2_D16 52
+#define CLK_TOP_LVDSPLL 53
+#define CLK_TOP_LVDSPLL_D2 54
+#define CLK_TOP_LVDSPLL_D4 55
+#define CLK_TOP_LVDSPLL_D8 56
+#define CLK_TOP_LVDSPLL2 57
+#define CLK_TOP_LVDSPLL2_D2 58
+#define CLK_TOP_LVDSPLL2_D4 59
+#define CLK_TOP_LVDSPLL2_D8 60
+#define CLK_TOP_ETHERPLL_125M 61
+#define CLK_TOP_ETHERPLL_50M 62
+#define CLK_TOP_CVBS 63
+#define CLK_TOP_CVBS_D2 64
+#define CLK_TOP_SYS_26M 65
+#define CLK_TOP_MMPLL 66
+#define CLK_TOP_MMPLL_D2 67
+#define CLK_TOP_VENCPLL 68
+#define CLK_TOP_VENCPLL_D2 69
+#define CLK_TOP_VCODECPLL 70
+#define CLK_TOP_VCODECPLL_D2 71
+#define CLK_TOP_TVDPLL 72
+#define CLK_TOP_TVDPLL_D2 73
+#define CLK_TOP_TVDPLL_D4 74
+#define CLK_TOP_TVDPLL_D8 75
+#define CLK_TOP_TVDPLL_429M 76
+#define CLK_TOP_TVDPLL_429M_D2 77
+#define CLK_TOP_TVDPLL_429M_D4 78
+#define CLK_TOP_MSDCPLL 79
+#define CLK_TOP_MSDCPLL_D2 80
+#define CLK_TOP_MSDCPLL_D4 81
+#define CLK_TOP_MSDCPLL2 82
+#define CLK_TOP_MSDCPLL2_D2 83
+#define CLK_TOP_MSDCPLL2_D4 84
+#define CLK_TOP_CLK26M_D2 85
+#define CLK_TOP_D2A_ULCLK_6P5M 86
+#define CLK_TOP_VPLL3_DPIX 87
+#define CLK_TOP_VPLL_DPIX 88
+#define CLK_TOP_LTEPLL_FS26M 89
+#define CLK_TOP_DMPLL 90
+#define CLK_TOP_DSI0_LNTC 91
+#define CLK_TOP_DSI1_LNTC 92
+#define CLK_TOP_LVDSTX3_CLKDIG_CTS 93
+#define CLK_TOP_LVDSTX_CLKDIG_CTS 94
+#define CLK_TOP_CLKRTC_EXT 95
+#define CLK_TOP_CLKRTC_INT 96
+#define CLK_TOP_CSI0 97
+#define CLK_TOP_CVBSPLL 98
+#define CLK_TOP_AXI_SEL 99
+#define CLK_TOP_MEM_SEL 100
+#define CLK_TOP_MM_SEL 101
+#define CLK_TOP_PWM_SEL 102
+#define CLK_TOP_VDEC_SEL 103
+#define CLK_TOP_VENC_SEL 104
+#define CLK_TOP_MFG_SEL 105
+#define CLK_TOP_CAMTG_SEL 106
+#define CLK_TOP_UART_SEL 107
+#define CLK_TOP_SPI_SEL 108
+#define CLK_TOP_USB20_SEL 109
+#define CLK_TOP_USB30_SEL 110
+#define CLK_TOP_MSDC50_0_HCLK_SEL 111
+#define CLK_TOP_MSDC50_0_SEL 112
+#define CLK_TOP_MSDC30_1_SEL 113
+#define CLK_TOP_MSDC30_2_SEL 114
+#define CLK_TOP_MSDC30_3_SEL 115
+#define CLK_TOP_AUDIO_SEL 116
+#define CLK_TOP_AUD_INTBUS_SEL 117
+#define CLK_TOP_PMICSPI_SEL 118
+#define CLK_TOP_DPILVDS1_SEL 119
+#define CLK_TOP_ATB_SEL 120
+#define CLK_TOP_NR_SEL 121
+#define CLK_TOP_NFI2X_SEL 122
+#define CLK_TOP_IRDA_SEL 123
+#define CLK_TOP_CCI400_SEL 124
+#define CLK_TOP_AUD_1_SEL 125
+#define CLK_TOP_AUD_2_SEL 126
+#define CLK_TOP_MEM_MFG_IN_AS_SEL 127
+#define CLK_TOP_AXI_MFG_IN_AS_SEL 128
+#define CLK_TOP_SCAM_SEL 129
+#define CLK_TOP_NFIECC_SEL 130
+#define CLK_TOP_PE2_MAC_P0_SEL 131
+#define CLK_TOP_PE2_MAC_P1_SEL 132
+#define CLK_TOP_DPILVDS_SEL 133
+#define CLK_TOP_MSDC50_3_HCLK_SEL 134
+#define CLK_TOP_HDCP_SEL 135
+#define CLK_TOP_HDCP_24M_SEL 136
+#define CLK_TOP_RTC_SEL 137
+#define CLK_TOP_SPINOR_SEL 138
+#define CLK_TOP_APLL_SEL 139
+#define CLK_TOP_APLL2_SEL 140
+#define CLK_TOP_A1SYS_HP_SEL 141
+#define CLK_TOP_A2SYS_HP_SEL 142
+#define CLK_TOP_ASM_L_SEL 143
+#define CLK_TOP_ASM_M_SEL 144
+#define CLK_TOP_ASM_H_SEL 145
+#define CLK_TOP_I2SO1_SEL 146
+#define CLK_TOP_I2SO2_SEL 147
+#define CLK_TOP_I2SO3_SEL 148
+#define CLK_TOP_TDMO0_SEL 149
+#define CLK_TOP_TDMO1_SEL 150
+#define CLK_TOP_I2SI1_SEL 151
+#define CLK_TOP_I2SI2_SEL 152
+#define CLK_TOP_I2SI3_SEL 153
+#define CLK_TOP_ETHER_125M_SEL 154
+#define CLK_TOP_ETHER_50M_SEL 155
+#define CLK_TOP_JPGDEC_SEL 156
+#define CLK_TOP_SPISLV_SEL 157
+#define CLK_TOP_ETHER_50M_RMII_SEL 158
+#define CLK_TOP_CAM2TG_SEL 159
+#define CLK_TOP_DI_SEL 160
+#define CLK_TOP_TVD_SEL 161
+#define CLK_TOP_I2C_SEL 162
+#define CLK_TOP_PWM_INFRA_SEL 163
+#define CLK_TOP_MSDC0P_AES_SEL 164
+#define CLK_TOP_CMSYS_SEL 165
+#define CLK_TOP_GCPU_SEL 166
+#define CLK_TOP_AUD_APLL1_SEL 167
+#define CLK_TOP_AUD_APLL2_SEL 168
+#define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 169
+#define CLK_TOP_APLL_DIV0 170
+#define CLK_TOP_APLL_DIV1 171
+#define CLK_TOP_APLL_DIV2 172
+#define CLK_TOP_APLL_DIV3 173
+#define CLK_TOP_APLL_DIV4 174
+#define CLK_TOP_APLL_DIV5 175
+#define CLK_TOP_APLL_DIV6 176
+#define CLK_TOP_APLL_DIV7 177
+#define CLK_TOP_APLL_DIV_PDN0 178
+#define CLK_TOP_APLL_DIV_PDN1 179
+#define CLK_TOP_APLL_DIV_PDN2 180
+#define CLK_TOP_APLL_DIV_PDN3 181
+#define CLK_TOP_APLL_DIV_PDN4 182
+#define CLK_TOP_APLL_DIV_PDN5 183
+#define CLK_TOP_APLL_DIV_PDN6 184
+#define CLK_TOP_APLL_DIV_PDN7 185
+#define CLK_TOP_NR_CLK 186
+
+/* INFRACFG */
+
+#define CLK_INFRA_DBGCLK 0
+#define CLK_INFRA_GCE 1
+#define CLK_INFRA_M4U 2
+#define CLK_INFRA_KP 3
+#define CLK_INFRA_AO_SPI0 4
+#define CLK_INFRA_AO_SPI1 5
+#define CLK_INFRA_AO_UART5 6
+#define CLK_INFRA_NR_CLK 7
+
+/* PERICFG */
+
+#define CLK_PERI_NFI 0
+#define CLK_PERI_THERM 1
+#define CLK_PERI_PWM0 2
+#define CLK_PERI_PWM1 3
+#define CLK_PERI_PWM2 4
+#define CLK_PERI_PWM3 5
+#define CLK_PERI_PWM4 6
+#define CLK_PERI_PWM5 7
+#define CLK_PERI_PWM6 8
+#define CLK_PERI_PWM7 9
+#define CLK_PERI_PWM 10
+#define CLK_PERI_AP_DMA 11
+#define CLK_PERI_MSDC30_0 12
+#define CLK_PERI_MSDC30_1 13
+#define CLK_PERI_MSDC30_2 14
+#define CLK_PERI_MSDC30_3 15
+#define CLK_PERI_UART0 16
+#define CLK_PERI_UART1 17
+#define CLK_PERI_UART2 18
+#define CLK_PERI_UART3 19
+#define CLK_PERI_I2C0 20
+#define CLK_PERI_I2C1 21
+#define CLK_PERI_I2C2 22
+#define CLK_PERI_I2C3 23
+#define CLK_PERI_I2C4 24
+#define CLK_PERI_AUXADC 25
+#define CLK_PERI_SPI0 26
+#define CLK_PERI_SPI 27
+#define CLK_PERI_I2C5 28
+#define CLK_PERI_SPI2 29
+#define CLK_PERI_SPI3 30
+#define CLK_PERI_SPI5 31
+#define CLK_PERI_UART4 32
+#define CLK_PERI_SFLASH 33
+#define CLK_PERI_GMAC 34
+#define CLK_PERI_PCIE0 35
+#define CLK_PERI_PCIE1 36
+#define CLK_PERI_GMAC_PCLK 37
+#define CLK_PERI_MSDC50_0_EN 38
+#define CLK_PERI_MSDC30_1_EN 39
+#define CLK_PERI_MSDC30_2_EN 40
+#define CLK_PERI_MSDC30_3_EN 41
+#define CLK_PERI_MSDC50_0_HCLK_EN 42
+#define CLK_PERI_MSDC50_3_HCLK_EN 43
+#define CLK_PERI_NR_CLK 44
+
+/* MCUCFG */
+
+#define CLK_MCU_MP0_SEL 0
+#define CLK_MCU_MP2_SEL 1
+#define CLK_MCU_BUS_SEL 2
+#define CLK_MCU_NR_CLK 3
+
+/* MFGCFG */
+
+#define CLK_MFG_BG3D 0
+#define CLK_MFG_NR_CLK 1
+
+/* MMSYS */
+
+#define CLK_MM_SMI_COMMON 0
+#define CLK_MM_SMI_LARB0 1
+#define CLK_MM_CAM_MDP 2
+#define CLK_MM_MDP_RDMA0 3
+#define CLK_MM_MDP_RDMA1 4
+#define CLK_MM_MDP_RSZ0 5
+#define CLK_MM_MDP_RSZ1 6
+#define CLK_MM_MDP_RSZ2 7
+#define CLK_MM_MDP_TDSHP0 8
+#define CLK_MM_MDP_TDSHP1 9
+#define CLK_MM_MDP_CROP 10
+#define CLK_MM_MDP_WDMA 11
+#define CLK_MM_MDP_WROT0 12
+#define CLK_MM_MDP_WROT1 13
+#define CLK_MM_FAKE_ENG 14
+#define CLK_MM_MUTEX_32K 15
+#define CLK_MM_DISP_OVL0 16
+#define CLK_MM_DISP_OVL1 17
+#define CLK_MM_DISP_RDMA0 18
+#define CLK_MM_DISP_RDMA1 19
+#define CLK_MM_DISP_RDMA2 20
+#define CLK_MM_DISP_WDMA0 21
+#define CLK_MM_DISP_WDMA1 22
+#define CLK_MM_DISP_COLOR0 23
+#define CLK_MM_DISP_COLOR1 24
+#define CLK_MM_DISP_AAL 25
+#define CLK_MM_DISP_GAMMA 26
+#define CLK_MM_DISP_UFOE 27
+#define CLK_MM_DISP_SPLIT0 28
+#define CLK_MM_DISP_OD 29
+#define CLK_MM_DISP_PWM0_MM 30
+#define CLK_MM_DISP_PWM0_26M 31
+#define CLK_MM_DISP_PWM1_MM 32
+#define CLK_MM_DISP_PWM1_26M 33
+#define CLK_MM_DSI0_ENGINE 34
+#define CLK_MM_DSI0_DIGITAL 35
+#define CLK_MM_DSI1_ENGINE 36
+#define CLK_MM_DSI1_DIGITAL 37
+#define CLK_MM_DPI_PIXEL 38
+#define CLK_MM_DPI_ENGINE 39
+#define CLK_MM_DPI1_PIXEL 40
+#define CLK_MM_DPI1_ENGINE 41
+#define CLK_MM_LVDS_PIXEL 42
+#define CLK_MM_LVDS_CTS 43
+#define CLK_MM_SMI_LARB4 44
+#define CLK_MM_SMI_COMMON1 45
+#define CLK_MM_SMI_LARB5 46
+#define CLK_MM_MDP_RDMA2 47
+#define CLK_MM_MDP_TDSHP2 48
+#define CLK_MM_DISP_OVL2 49
+#define CLK_MM_DISP_WDMA2 50
+#define CLK_MM_DISP_COLOR2 51
+#define CLK_MM_DISP_AAL1 52
+#define CLK_MM_DISP_OD1 53
+#define CLK_MM_LVDS1_PIXEL 54
+#define CLK_MM_LVDS1_CTS 55
+#define CLK_MM_SMI_LARB7 56
+#define CLK_MM_MDP_RDMA3 57
+#define CLK_MM_MDP_WROT2 58
+#define CLK_MM_DSI2 59
+#define CLK_MM_DSI2_DIGITAL 60
+#define CLK_MM_DSI3 61
+#define CLK_MM_DSI3_DIGITAL 62
+#define CLK_MM_NR_CLK 63
+
+/* IMGSYS */
+
+#define CLK_IMG_SMI_LARB2 0
+#define CLK_IMG_SENINF_SCAM_EN 1
+#define CLK_IMG_SENINF_CAM_EN 2
+#define CLK_IMG_CAM_SV_EN 3
+#define CLK_IMG_CAM_SV1_EN 4
+#define CLK_IMG_CAM_SV2_EN 5
+#define CLK_IMG_NR_CLK 6
+
+/* BDPSYS */
+
+#define CLK_BDP_BRIDGE_B 0
+#define CLK_BDP_BRIDGE_DRAM 1
+#define CLK_BDP_LARB_DRAM 2
+#define CLK_BDP_WR_CHANNEL_VDI_PXL 3
+#define CLK_BDP_WR_CHANNEL_VDI_DRAM 4
+#define CLK_BDP_WR_CHANNEL_VDI_B 5
+#define CLK_BDP_MT_B 6
+#define CLK_BDP_DISPFMT_27M 7
+#define CLK_BDP_DISPFMT_27M_VDOUT 8
+#define CLK_BDP_DISPFMT_27_74_74 9
+#define CLK_BDP_DISPFMT_2FS 10
+#define CLK_BDP_DISPFMT_2FS_2FS74_148 11
+#define CLK_BDP_DISPFMT_B 12
+#define CLK_BDP_VDO_DRAM 13
+#define CLK_BDP_VDO_2FS 14
+#define CLK_BDP_VDO_B 15
+#define CLK_BDP_WR_CHANNEL_DI_PXL 16
+#define CLK_BDP_WR_CHANNEL_DI_DRAM 17
+#define CLK_BDP_WR_CHANNEL_DI_B 18
+#define CLK_BDP_NR_AGENT 19
+#define CLK_BDP_NR_DRAM 20
+#define CLK_BDP_NR_B 21
+#define CLK_BDP_BRIDGE_RT_B 22
+#define CLK_BDP_BRIDGE_RT_DRAM 23
+#define CLK_BDP_LARB_RT_DRAM 24
+#define CLK_BDP_TVD_TDC 25
+#define CLK_BDP_TVD_54 26
+#define CLK_BDP_TVD_CBUS 27
+#define CLK_BDP_NR_CLK 28
+
+/* VDECSYS */
+
+#define CLK_VDEC_CKEN 0
+#define CLK_VDEC_LARB1_CKEN 1
+#define CLK_VDEC_IMGRZ_CKEN 2
+#define CLK_VDEC_NR_CLK 3
+
+/* VENCSYS */
+
+#define CLK_VENC_SMI_COMMON_CON 0
+#define CLK_VENC_VENC 1
+#define CLK_VENC_SMI_LARB6 2
+#define CLK_VENC_NR_CLK 3
+
+/* JPGDECSYS */
+
+#define CLK_JPGDEC_JPGDEC1 0
+#define CLK_JPGDEC_JPGDEC 1
+#define CLK_JPGDEC_NR_CLK 2
+
+#endif /* _DT_BINDINGS_CLK_MT2712_H */
diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h
new file mode 100644
index 000000000000..3e514ed51d15
--- /dev/null
+++ b/include/dt-bindings/clock/mt7622-clk.h
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Chen Zhong <chen.zhong@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7622_H
+#define _DT_BINDINGS_CLK_MT7622_H
+
+/* TOPCKGEN */
+
+#define CLK_TOP_TO_U2_PHY 0
+#define CLK_TOP_TO_U2_PHY_1P 1
+#define CLK_TOP_PCIE0_PIPE_EN 2
+#define CLK_TOP_PCIE1_PIPE_EN 3
+#define CLK_TOP_SSUSB_TX250M 4
+#define CLK_TOP_SSUSB_EQ_RX250M 5
+#define CLK_TOP_SSUSB_CDR_REF 6
+#define CLK_TOP_SSUSB_CDR_FB 7
+#define CLK_TOP_SATA_ASIC 8
+#define CLK_TOP_SATA_RBC 9
+#define CLK_TOP_TO_USB3_SYS 10
+#define CLK_TOP_P1_1MHZ 11
+#define CLK_TOP_4MHZ 12
+#define CLK_TOP_P0_1MHZ 13
+#define CLK_TOP_TXCLK_SRC_PRE 14
+#define CLK_TOP_RTC 15
+#define CLK_TOP_MEMPLL 16
+#define CLK_TOP_DMPLL 17
+#define CLK_TOP_SYSPLL_D2 18
+#define CLK_TOP_SYSPLL1_D2 19
+#define CLK_TOP_SYSPLL1_D4 20
+#define CLK_TOP_SYSPLL1_D8 21
+#define CLK_TOP_SYSPLL2_D4 22
+#define CLK_TOP_SYSPLL2_D8 23
+#define CLK_TOP_SYSPLL_D5 24
+#define CLK_TOP_SYSPLL3_D2 25
+#define CLK_TOP_SYSPLL3_D4 26
+#define CLK_TOP_SYSPLL4_D2 27
+#define CLK_TOP_SYSPLL4_D4 28
+#define CLK_TOP_SYSPLL4_D16 29
+#define CLK_TOP_UNIVPLL 30
+#define CLK_TOP_UNIVPLL_D2 31
+#define CLK_TOP_UNIVPLL1_D2 32
+#define CLK_TOP_UNIVPLL1_D4 33
+#define CLK_TOP_UNIVPLL1_D8 34
+#define CLK_TOP_UNIVPLL1_D16 35
+#define CLK_TOP_UNIVPLL2_D2 36
+#define CLK_TOP_UNIVPLL2_D4 37
+#define CLK_TOP_UNIVPLL2_D8 38
+#define CLK_TOP_UNIVPLL2_D16 39
+#define CLK_TOP_UNIVPLL_D5 40
+#define CLK_TOP_UNIVPLL3_D2 41
+#define CLK_TOP_UNIVPLL3_D4 42
+#define CLK_TOP_UNIVPLL3_D16 43
+#define CLK_TOP_UNIVPLL_D7 44
+#define CLK_TOP_UNIVPLL_D80_D4 45
+#define CLK_TOP_UNIV48M 46
+#define CLK_TOP_SGMIIPLL 47
+#define CLK_TOP_SGMIIPLL_D2 48
+#define CLK_TOP_AUD1PLL 49
+#define CLK_TOP_AUD2PLL 50
+#define CLK_TOP_AUD_I2S2_MCK 51
+#define CLK_TOP_TO_USB3_REF 52
+#define CLK_TOP_PCIE1_MAC_EN 53
+#define CLK_TOP_PCIE0_MAC_EN 54
+#define CLK_TOP_ETH_500M 55
+#define CLK_TOP_AXI_SEL 56
+#define CLK_TOP_MEM_SEL 57
+#define CLK_TOP_DDRPHYCFG_SEL 58
+#define CLK_TOP_ETH_SEL 59
+#define CLK_TOP_PWM_SEL 60
+#define CLK_TOP_F10M_REF_SEL 61
+#define CLK_TOP_NFI_INFRA_SEL 62
+#define CLK_TOP_FLASH_SEL 63
+#define CLK_TOP_UART_SEL 64
+#define CLK_TOP_SPI0_SEL 65
+#define CLK_TOP_SPI1_SEL 66
+#define CLK_TOP_MSDC50_0_SEL 67
+#define CLK_TOP_MSDC30_0_SEL 68
+#define CLK_TOP_MSDC30_1_SEL 69
+#define CLK_TOP_A1SYS_HP_SEL 70
+#define CLK_TOP_A2SYS_HP_SEL 71
+#define CLK_TOP_INTDIR_SEL 72
+#define CLK_TOP_AUD_INTBUS_SEL 73
+#define CLK_TOP_PMICSPI_SEL 74
+#define CLK_TOP_SCP_SEL 75
+#define CLK_TOP_ATB_SEL 76
+#define CLK_TOP_HIF_SEL 77
+#define CLK_TOP_AUDIO_SEL 78
+#define CLK_TOP_U2_SEL 79
+#define CLK_TOP_AUD1_SEL 80
+#define CLK_TOP_AUD2_SEL 81
+#define CLK_TOP_IRRX_SEL 82
+#define CLK_TOP_IRTX_SEL 83
+#define CLK_TOP_ASM_L_SEL 84
+#define CLK_TOP_ASM_M_SEL 85
+#define CLK_TOP_ASM_H_SEL 86
+#define CLK_TOP_APLL1_SEL 87
+#define CLK_TOP_APLL2_SEL 88
+#define CLK_TOP_I2S0_MCK_SEL 89
+#define CLK_TOP_I2S1_MCK_SEL 90
+#define CLK_TOP_I2S2_MCK_SEL 91
+#define CLK_TOP_I2S3_MCK_SEL 92
+#define CLK_TOP_APLL1_DIV 93
+#define CLK_TOP_APLL2_DIV 94
+#define CLK_TOP_I2S0_MCK_DIV 95
+#define CLK_TOP_I2S1_MCK_DIV 96
+#define CLK_TOP_I2S2_MCK_DIV 97
+#define CLK_TOP_I2S3_MCK_DIV 98
+#define CLK_TOP_A1SYS_HP_DIV 99
+#define CLK_TOP_A2SYS_HP_DIV 100
+#define CLK_TOP_APLL1_DIV_PD 101
+#define CLK_TOP_APLL2_DIV_PD 102
+#define CLK_TOP_I2S0_MCK_DIV_PD 103
+#define CLK_TOP_I2S1_MCK_DIV_PD 104
+#define CLK_TOP_I2S2_MCK_DIV_PD 105
+#define CLK_TOP_I2S3_MCK_DIV_PD 106
+#define CLK_TOP_A1SYS_HP_DIV_PD 107
+#define CLK_TOP_A2SYS_HP_DIV_PD 108
+#define CLK_TOP_NR_CLK 109
+
+/* INFRACFG */
+
+#define CLK_INFRA_MUX1_SEL 0
+#define CLK_INFRA_DBGCLK_PD 1
+#define CLK_INFRA_AUDIO_PD 2
+#define CLK_INFRA_IRRX_PD 3
+#define CLK_INFRA_APXGPT_PD 4
+#define CLK_INFRA_PMIC_PD 5
+#define CLK_INFRA_TRNG 6
+#define CLK_INFRA_NR_CLK 7
+
+/* PERICFG */
+
+#define CLK_PERIBUS_SEL 0
+#define CLK_PERI_THERM_PD 1
+#define CLK_PERI_PWM1_PD 2
+#define CLK_PERI_PWM2_PD 3
+#define CLK_PERI_PWM3_PD 4
+#define CLK_PERI_PWM4_PD 5
+#define CLK_PERI_PWM5_PD 6
+#define CLK_PERI_PWM6_PD 7
+#define CLK_PERI_PWM7_PD 8
+#define CLK_PERI_PWM_PD 9
+#define CLK_PERI_AP_DMA_PD 10
+#define CLK_PERI_MSDC30_0_PD 11
+#define CLK_PERI_MSDC30_1_PD 12
+#define CLK_PERI_UART0_PD 13
+#define CLK_PERI_UART1_PD 14
+#define CLK_PERI_UART2_PD 15
+#define CLK_PERI_UART3_PD 16
+#define CLK_PERI_UART4_PD 17
+#define CLK_PERI_BTIF_PD 18
+#define CLK_PERI_I2C0_PD 19
+#define CLK_PERI_I2C1_PD 20
+#define CLK_PERI_I2C2_PD 21
+#define CLK_PERI_SPI1_PD 22
+#define CLK_PERI_AUXADC_PD 23
+#define CLK_PERI_SPI0_PD 24
+#define CLK_PERI_SNFI_PD 25
+#define CLK_PERI_NFI_PD 26
+#define CLK_PERI_NFIECC_PD 27
+#define CLK_PERI_FLASH_PD 28
+#define CLK_PERI_IRTX_PD 29
+#define CLK_PERI_NR_CLK 30
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL 0
+#define CLK_APMIXED_MAINPLL 1
+#define CLK_APMIXED_UNIV2PLL 2
+#define CLK_APMIXED_ETH1PLL 3
+#define CLK_APMIXED_ETH2PLL 4
+#define CLK_APMIXED_AUD1PLL 5
+#define CLK_APMIXED_AUD2PLL 6
+#define CLK_APMIXED_TRGPLL 7
+#define CLK_APMIXED_SGMIPLL 8
+#define CLK_APMIXED_MAIN_CORE_EN 9
+#define CLK_APMIXED_NR_CLK 10
+
+/* AUDIOSYS */
+
+#define CLK_AUDIO_AFE 0
+#define CLK_AUDIO_HDMI 1
+#define CLK_AUDIO_SPDF 2
+#define CLK_AUDIO_APLL 3
+#define CLK_AUDIO_I2SIN1 4
+#define CLK_AUDIO_I2SIN2 5
+#define CLK_AUDIO_I2SIN3 6
+#define CLK_AUDIO_I2SIN4 7
+#define CLK_AUDIO_I2SO1 8
+#define CLK_AUDIO_I2SO2 9
+#define CLK_AUDIO_I2SO3 10
+#define CLK_AUDIO_I2SO4 11
+#define CLK_AUDIO_ASRCI1 12
+#define CLK_AUDIO_ASRCI2 13
+#define CLK_AUDIO_ASRCO1 14
+#define CLK_AUDIO_ASRCO2 15
+#define CLK_AUDIO_INTDIR 16
+#define CLK_AUDIO_A1SYS 17
+#define CLK_AUDIO_A2SYS 18
+#define CLK_AUDIO_UL1 19
+#define CLK_AUDIO_UL2 20
+#define CLK_AUDIO_UL3 21
+#define CLK_AUDIO_UL4 22
+#define CLK_AUDIO_UL5 23
+#define CLK_AUDIO_UL6 24
+#define CLK_AUDIO_DL1 25
+#define CLK_AUDIO_DL2 26
+#define CLK_AUDIO_DL3 27
+#define CLK_AUDIO_DL4 28
+#define CLK_AUDIO_DL5 29
+#define CLK_AUDIO_DL6 30
+#define CLK_AUDIO_DLMCH 31
+#define CLK_AUDIO_ARB1 32
+#define CLK_AUDIO_AWB 33
+#define CLK_AUDIO_AWB2 34
+#define CLK_AUDIO_DAI 35
+#define CLK_AUDIO_MOD 36
+#define CLK_AUDIO_ASRCI3 37
+#define CLK_AUDIO_ASRCI4 38
+#define CLK_AUDIO_ASRCO3 39
+#define CLK_AUDIO_ASRCO4 40
+#define CLK_AUDIO_MEM_ASRC1 41
+#define CLK_AUDIO_MEM_ASRC2 42
+#define CLK_AUDIO_MEM_ASRC3 43
+#define CLK_AUDIO_MEM_ASRC4 44
+#define CLK_AUDIO_MEM_ASRC5 45
+#define CLK_AUDIO_NR_CLK 46
+
+/* SSUSBSYS */
+
+#define CLK_SSUSB_U2_PHY_1P_EN 0
+#define CLK_SSUSB_U2_PHY_EN 1
+#define CLK_SSUSB_REF_EN 2
+#define CLK_SSUSB_SYS_EN 3
+#define CLK_SSUSB_MCU_EN 4
+#define CLK_SSUSB_DMA_EN 5
+#define CLK_SSUSB_NR_CLK 6
+
+/* PCIESYS */
+
+#define CLK_PCIE_P1_AUX_EN 0
+#define CLK_PCIE_P1_OBFF_EN 1
+#define CLK_PCIE_P1_AHB_EN 2
+#define CLK_PCIE_P1_AXI_EN 3
+#define CLK_PCIE_P1_MAC_EN 4
+#define CLK_PCIE_P1_PIPE_EN 5
+#define CLK_PCIE_P0_AUX_EN 6
+#define CLK_PCIE_P0_OBFF_EN 7
+#define CLK_PCIE_P0_AHB_EN 8
+#define CLK_PCIE_P0_AXI_EN 9
+#define CLK_PCIE_P0_MAC_EN 10
+#define CLK_PCIE_P0_PIPE_EN 11
+#define CLK_SATA_AHB_EN 12
+#define CLK_SATA_AXI_EN 13
+#define CLK_SATA_ASIC_EN 14
+#define CLK_SATA_RBC_EN 15
+#define CLK_SATA_PM_EN 16
+#define CLK_PCIE_NR_CLK 17
+
+/* ETHSYS */
+
+#define CLK_ETH_HSDMA_EN 0
+#define CLK_ETH_ESW_EN 1
+#define CLK_ETH_GP2_EN 2
+#define CLK_ETH_GP1_EN 3
+#define CLK_ETH_GP0_EN 4
+#define CLK_ETH_NR_CLK 5
+
+/* SGMIISYS */
+
+#define CLK_SGMII_TX250M_EN 0
+#define CLK_SGMII_RX250M_EN 1
+#define CLK_SGMII_CDR_REF 2
+#define CLK_SGMII_CDR_FB 3
+#define CLK_SGMII_NR_CLK 4
+
+#endif /* _DT_BINDINGS_CLK_MT7622_H */
+
diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h
index 96b63c00249e..b8337a5fa347 100644
--- a/include/dt-bindings/clock/qcom,rpmcc.h
+++ b/include/dt-bindings/clock/qcom,rpmcc.h
@@ -37,6 +37,9 @@
#define RPM_SYS_FABRIC_A_CLK 19
#define RPM_SFPB_CLK 20
#define RPM_SFPB_A_CLK 21
+#define RPM_SMI_CLK 22
+#define RPM_SMI_A_CLK 23
+#define RPM_PLL4_CLK 24
/* SMD RPM clocks */
#define RPM_SMD_XO_CLK_SRC 0
@@ -101,5 +104,19 @@
#define RPM_SMD_CXO_A1_A_PIN 59
#define RPM_SMD_CXO_A2_PIN 60
#define RPM_SMD_CXO_A2_A_PIN 61
+#define RPM_SMD_AGGR1_NOC_CLK 62
+#define RPM_SMD_AGGR1_NOC_A_CLK 63
+#define RPM_SMD_AGGR2_NOC_CLK 64
+#define RPM_SMD_AGGR2_NOC_A_CLK 65
+#define RPM_SMD_MMAXI_CLK 66
+#define RPM_SMD_MMAXI_A_CLK 67
+#define RPM_SMD_IPA_CLK 68
+#define RPM_SMD_IPA_A_CLK 69
+#define RPM_SMD_CE1_CLK 70
+#define RPM_SMD_CE1_A_CLK 71
+#define RPM_SMD_DIV_CLK3 72
+#define RPM_SMD_DIV_A_CLK3 73
+#define RPM_SMD_LN_BB_CLK 74
+#define RPM_SMD_LN_BB_A_CLK 75
#endif
diff --git a/include/dt-bindings/clock/r8a77970-cpg-mssr.h b/include/dt-bindings/clock/r8a77970-cpg-mssr.h
new file mode 100644
index 000000000000..4146395595b1
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77970-cpg-mssr.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77970 CPG Core Clocks */
+#define R8A77970_CLK_Z2 0
+#define R8A77970_CLK_ZR 1
+#define R8A77970_CLK_ZTR 2
+#define R8A77970_CLK_ZTRD2 3
+#define R8A77970_CLK_ZT 4
+#define R8A77970_CLK_ZX 5
+#define R8A77970_CLK_S1D1 6
+#define R8A77970_CLK_S1D2 7
+#define R8A77970_CLK_S1D4 8
+#define R8A77970_CLK_S2D1 9
+#define R8A77970_CLK_S2D2 10
+#define R8A77970_CLK_S2D4 11
+#define R8A77970_CLK_LB 12
+#define R8A77970_CLK_CL 13
+#define R8A77970_CLK_ZB3 14
+#define R8A77970_CLK_ZB3D2 15
+#define R8A77970_CLK_DDR 16
+#define R8A77970_CLK_CR 17
+#define R8A77970_CLK_CRD2 18
+#define R8A77970_CLK_SD0H 19
+#define R8A77970_CLK_SD0 20
+#define R8A77970_CLK_RPC 21
+#define R8A77970_CLK_RPCD2 22
+#define R8A77970_CLK_MSO 23
+#define R8A77970_CLK_CANFD 24
+#define R8A77970_CLK_CSI0 25
+#define R8A77970_CLK_FRAY 26
+#define R8A77970_CLK_CP 27
+#define R8A77970_CLK_CPEX 28
+#define R8A77970_CLK_R 29
+#define R8A77970_CLK_OSC 30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/s3c2443.h b/include/dt-bindings/clock/s3c2443.h
index 37e66b054d64..f3ba68a25ecb 100644
--- a/include/dt-bindings/clock/s3c2443.h
+++ b/include/dt-bindings/clock/s3c2443.h
@@ -26,6 +26,8 @@
#define ARMCLK 4
#define HCLK 5
#define PCLK 6
+#define MPLL 7
+#define EPLL 8
/* Special clocks */
#define SCLK_HSSPI0 16
diff --git a/include/dt-bindings/clock/sun4i-a10-ccu.h b/include/dt-bindings/clock/sun4i-a10-ccu.h
index c5a53f38d654..e4fa61be5c75 100644
--- a/include/dt-bindings/clock/sun4i-a10-ccu.h
+++ b/include/dt-bindings/clock/sun4i-a10-ccu.h
@@ -43,6 +43,8 @@
#define _DT_BINDINGS_CLK_SUN4I_A10_H_
#define CLK_HOSC 1
+#define CLK_PLL_VIDEO0_2X 9
+#define CLK_PLL_VIDEO1_2X 18
#define CLK_CPU 20
/* AHB Gates */
diff --git a/include/dt-bindings/clock/sun6i-a31-ccu.h b/include/dt-bindings/clock/sun6i-a31-ccu.h
index 4482530fb6f5..c5d13340184a 100644
--- a/include/dt-bindings/clock/sun6i-a31-ccu.h
+++ b/include/dt-bindings/clock/sun6i-a31-ccu.h
@@ -43,8 +43,12 @@
#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_
#define _DT_BINDINGS_CLK_SUN6I_A31_H_
+#define CLK_PLL_VIDEO0_2X 7
+
#define CLK_PLL_PERIPH 10
+#define CLK_PLL_VIDEO1_2X 13
+
#define CLK_CPU 18
#define CLK_AHB1_MIPIDSI 23
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 5100ec1b5d55..7c925e6211f1 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -682,10 +682,10 @@ struct clk_gpio {
extern const struct clk_ops clk_gpio_gate_ops;
struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
- const char *parent_name, unsigned gpio, bool active_low,
+ const char *parent_name, struct gpio_desc *gpiod,
unsigned long flags);
struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name,
- const char *parent_name, unsigned gpio, bool active_low,
+ const char *parent_name, struct gpio_desc *gpiod,
unsigned long flags);
void clk_hw_unregister_gpio_gate(struct clk_hw *hw);
@@ -701,11 +701,11 @@ void clk_hw_unregister_gpio_gate(struct clk_hw *hw);
extern const struct clk_ops clk_gpio_mux_ops;
struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
- const char * const *parent_names, u8 num_parents, unsigned gpio,
- bool active_low, unsigned long flags);
+ const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
+ unsigned long flags);
struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name,
- const char * const *parent_names, u8 num_parents, unsigned gpio,
- bool active_low, unsigned long flags);
+ const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
+ unsigned long flags);
void clk_hw_unregister_gpio_mux(struct clk_hw *hw);
/**
@@ -815,7 +815,12 @@ int of_clk_add_hw_provider(struct device_node *np,
struct clk_hw *(*get)(struct of_phandle_args *clkspec,
void *data),
void *data);
+int devm_of_clk_add_hw_provider(struct device *dev,
+ struct clk_hw *(*get)(struct of_phandle_args *clkspec,
+ void *data),
+ void *data);
void of_clk_del_provider(struct device_node *np);
+void devm_of_clk_del_provider(struct device *dev);
struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
void *data);
struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
@@ -847,7 +852,15 @@ static inline int of_clk_add_hw_provider(struct device_node *np,
{
return 0;
}
+static inline int devm_of_clk_add_hw_provider(struct device *dev,
+ struct clk_hw *(*get)(struct of_phandle_args *clkspec,
+ void *data),
+ void *data)
+{
+ return 0;
+}
static inline void of_clk_del_provider(struct device_node *np) {}
+static inline void devm_of_clk_del_provider(struct device *dev) {}
static inline struct clk *of_clk_src_simple_get(
struct of_phandle_args *clkspec, void *data)
{
diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h
index 4eff6e68600d..9f5c6e53f3a5 100644
--- a/include/linux/soc/qcom/smd-rpm.h
+++ b/include/linux/soc/qcom/smd-rpm.h
@@ -27,6 +27,10 @@ struct qcom_smd_rpm;
#define QCOM_SMD_RPM_SMPB 0x62706d73
#define QCOM_SMD_RPM_SPDM 0x63707362
#define QCOM_SMD_RPM_VSA 0x00617376
+#define QCOM_SMD_RPM_MMAXI_CLK 0x69786d6d
+#define QCOM_SMD_RPM_IPA_CLK 0x617069
+#define QCOM_SMD_RPM_CE_CLK 0x6563
+#define QCOM_SMD_RPM_AGGR_CLK 0x72676761
int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,
int state,
diff --git a/include/soc/at91/atmel-sfr.h b/include/soc/at91/atmel-sfr.h
index 506ea8ffda19..482337af06b8 100644
--- a/include/soc/at91/atmel-sfr.h
+++ b/include/soc/at91/atmel-sfr.h
@@ -17,6 +17,7 @@
/* 0x08 ~ 0x0c: Reserved */
#define AT91_SFR_OHCIICR 0x10 /* OHCI INT Configuration Register */
#define AT91_SFR_OHCIISR 0x14 /* OHCI INT Status Register */
+#define AT91_SFR_UTMICKTRIM 0x30 /* UTMI Clock Trimming Register */
#define AT91_SFR_I2SCLKSEL 0x90 /* I2SC Register */
/* Field definitions */
@@ -28,5 +29,6 @@
AT91_OHCIICR_SUSPEND_B | \
AT91_OHCIICR_SUSPEND_C)
+#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0)
#endif /* _LINUX_MFD_SYSCON_ATMEL_SFR_H */