diff options
| author | Palmer Dabbelt <palmer@dabbelt.com> | 2018-01-29 10:25:23 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2018-01-29 10:25:23 -0800 |
| commit | ba9e25a62bd662ce8c7ed6c8d1c072110f1ffae5 (patch) | |
| tree | 3ef42adf948b0e4f65e39e21f5c4a49da7e0b34f | |
| parent | 4215e27674de95a564087a3841873f3d980d4764 (diff) | |
Add documentation for __riscv_flush_icache
This function is used by GCC to enforce ordering between data writes and
instruction fetches, and while we'd prefer that users rely on the GCC
intrinsic when possible this is user visible in case that's not
possible.
2018-01-29 Palmer Dabbelt <palmer@sifive.com>
* manual/platform.texi: Add RISC-V documenation for
__riscv_flush_icache.
| -rw-r--r-- | ChangeLog | 2 | ||||
| -rw-r--r-- | manual/platform.texi | 19 |
2 files changed, 21 insertions, 0 deletions
@@ -4,6 +4,8 @@ PREINIT_FUNCTION when defined. * manual/math.texi: RISC-V supports _Float128 and _Float64x. * config.h.in: Regenerate. + * manual/platform.texi: Add RISC-V documenation for + __riscv_flush_icache. 2018-01-29 Florian Weimer <fweimer@redhat.com> diff --git a/manual/platform.texi b/manual/platform.texi index cb166641fb..b8721a0712 100644 --- a/manual/platform.texi +++ b/manual/platform.texi @@ -6,6 +6,7 @@ @menu * PowerPC:: Facilities Specific to the PowerPC Architecture +* RISC-V:: Facilities Specific to the RISC-V Architecture @end menu @node PowerPC @@ -115,3 +116,21 @@ problem-state programs. If the program priority is medium high when the time interval expires or if an attempt is made to set the priority to medium high when it is not allowed, the priority is set to medium. @end deftypefun + +@node RISC-V +@appendixsec RISC-V-specific Facilities + +Cache management facilities specific to RISC-V systems that implement the Linux +ABI are declared in @file{sys/cachectl.h}. + +@deftypefun {void} __riscv_flush_icache(void *@var{start}, void *@var{end}, unsigned long int @var{flags}) +@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} +Enforce ordering between stores and instruction cache fetches. The range of +addresses over which ordering is enforced is specified by @var{start} and +@var{end}. The @var{flags} argument controls the extent of this ordering, with +the default behavior (a @var{flags} value of 0) being to enforce the fence on +all threads in the current process. Setting the +@code{SYS_RISCV_FLUSH_ICACHE_LOCAL} bit allows users to indicate that enforcing +ordering on only the current thread is necessary. All other flag bits are +reserved. +@end deftypefun |