From ba5a3780dd9937d0f3adee051239ea3aa65dd148 Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Date: Wed, 30 Apr 2014 16:11:08 +0200
Subject: aarch64: Fix and<mode>3_zeroextend case (20040709-1.s regression).

With the unguarded, HImode/QImode-optimized and-pattern, an additional
guard for the immediate bitmask is required to exclude cases where an
inverted bitmask is used (i.e. all-ones in those bits that should be
zero-extended).
---
 gcc/config/aarch64/aarch64.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index e3c493ae85e0..294eb5de596d 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -3443,12 +3443,12 @@
 )
 
 ;; zero_extend version of above
-(define_insn "*and<mode>3_zeroextend"
+(define_insn "*and<mode>3_zeroextend<ALLX:mode>"
   [(set (match_operand:GPI 0 "register_operand" "=r")
         (zero_extend:GPI
           (and:ALLX (match_operand:ALLX 1 "register_operand" "r")
                     (match_operand:ALLX 2 "const_int_operand" "<andconst>"))))]
-  ""
+  "UINTVAL(operands[2]) < (1 << GET_MODE_BITSIZE (<ALLX:MODE>mode))"
   "and\\t%w0, %w1, %w2"
   [(set_attr "type" "logic_imm")]
 )
-- 
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