diff options
| author | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2014-04-30 16:11:08 +0200 |
|---|---|---|
| committer | Christoph Muellner <christoph.muellner@theobroma-systems.com> | 2018-04-27 10:17:12 +0200 |
| commit | ba5a3780dd9937d0f3adee051239ea3aa65dd148 (patch) | |
| tree | 9cc3b4bf23b1909b5c45fda99b4a45a5f297fe6a | |
| parent | d7e5332c0809d246afdbe6e27c65ed4aae7005ac (diff) | |
aarch64: Fix and<mode>3_zeroextend case (20040709-1.s regression).
With the unguarded, HImode/QImode-optimized and-pattern, an additional
guard for the immediate bitmask is required to exclude cases where an
inverted bitmask is used (i.e. all-ones in those bits that should be
zero-extended).
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index e3c493ae85e0..294eb5de596d 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3443,12 +3443,12 @@ ) ;; zero_extend version of above -(define_insn "*and<mode>3_zeroextend" +(define_insn "*and<mode>3_zeroextend<ALLX:mode>" [(set (match_operand:GPI 0 "register_operand" "=r") (zero_extend:GPI (and:ALLX (match_operand:ALLX 1 "register_operand" "r") (match_operand:ALLX 2 "const_int_operand" "<andconst>"))))] - "" + "UINTVAL(operands[2]) < (1 << GET_MODE_BITSIZE (<ALLX:MODE>mode))" "and\\t%w0, %w1, %w2" [(set_attr "type" "logic_imm")] ) |