diff options
| author | rguenth <rguenth@138bc75d-0d04-0410-961f-82ee72b054a4> | 2018-01-16 09:51:57 +0000 |
|---|---|---|
| committer | rguenth <rguenth@138bc75d-0d04-0410-961f-82ee72b054a4> | 2018-01-16 09:51:57 +0000 |
| commit | 129bdef578ab7cf7edc18b142672b67936c4df80 (patch) | |
| tree | 7a3d35a2f18720433b15597cda51cdce788c3f0e | |
| parent | 1fe34f83fe7ade01d2087e2183f2924a16262133 (diff) | |
2018-01-16 Richard Biener <rguenther@suse.de>
Backport from mainline
2017-09-29 Vladimir Makarov <vmakarov@redhat.com>
PR target/81481
* ira-costs.c (scan_one_insn): Don't take into account PIC equiv
with a symbol for LRA.
* gcc.target/i386/pr81481.c: New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-7-branch@256731 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/ira-costs.c | 5 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr81481.c | 18 |
4 files changed, 39 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d74730bc5c0b..d2edaadec1df 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2018-01-16 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2017-09-29 Vladimir Makarov <vmakarov@redhat.com> + + PR target/81481 + * ira-costs.c (scan_one_insn): Don't take into account PIC equiv + with a symbol for LRA. + 2018-01-15 Segher Boessenkool <segher@kernel.crashing.org> Backport from mainline diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c index 9cf011942255..6b7cbcd37270 100644 --- a/gcc/ira-costs.c +++ b/gcc/ira-costs.c @@ -1485,7 +1485,10 @@ scan_one_insn (rtx_insn *insn) && targetm.legitimate_constant_p (GET_MODE (SET_DEST (set)), XEXP (note, 0)) && REG_N_SETS (REGNO (SET_DEST (set))) == 1)) - && general_operand (SET_SRC (set), GET_MODE (SET_SRC (set)))) + && general_operand (SET_SRC (set), GET_MODE (SET_SRC (set))) + /* LRA does not use equiv with a symbol for PIC code. */ + && (! ira_use_lra_p || ! pic_offset_table_rtx + || ! contains_symbol_ref_p (XEXP (note, 0)))) { enum reg_class cl = GENERAL_REGS; rtx reg = SET_DEST (set); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 1579cba53721..f124ce051957 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,11 @@ +2018-01-16 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2017-09-29 Vladimir Makarov <vmakarov@redhat.com> + + PR target/81481 + * gcc.target/i386/pr81481.c: New. + 2018-01-15 Segher Boessenkool <segher@kernel.crashing.org> Backport from mainline diff --git a/gcc/testsuite/gcc.target/i386/pr81481.c b/gcc/testsuite/gcc.target/i386/pr81481.c new file mode 100644 index 000000000000..a5b936fdacc1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81481.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ssse3 } */ +/* { dg-options "-O2 -fpic -mssse3" } */ +/* { dg-final { scan-assembler-not "pshufb\[ \t\]\\(%esp\\)" } } */ +#include <immintrin.h> + +extern const signed char c[31] __attribute__((visibility("hidden"))); + +__m128i f(__m128i *x, void *v) +{ + int i; + asm("# %0" : "=r"(i)); + __m128i t = _mm_loadu_si128((void*)&c[i]); + __m128i xx = *x; + xx = _mm_shuffle_epi8(xx, t); + asm("# %0 %1 %2" : "+x"(xx) : "r"(c), "r"(i)); + return xx; +} |