diff options
| author | Martin Storsjo <martin@martin.st> | 2018-01-24 10:14:52 +0000 |
|---|---|---|
| committer | Martin Storsjo <martin@martin.st> | 2018-01-24 10:14:52 +0000 |
| commit | e5e86e7561832cd4c672a699fe2a484a8e2680ef (patch) | |
| tree | e522c16c0e0d2b7cb3d4984faebc27b4d406133f /lib/builtins/clear_cache.c | |
| parent | a3840a49f924073c9f6fd5abbb7a894b5f790cad (diff) | |
[builtins] Align addresses to cache lines in __clear_cache for aarch64
This makes sure that the last cache line gets invalidated properly.
This matches the example code at
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/BABJDBHI.html,
and also matches what libgcc does.
Differential Revision: https://reviews.llvm.org/D42196
git-svn-id: https://llvm.org/svn/llvm-project/compiler-rt/trunk@323315 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/builtins/clear_cache.c')
| -rw-r--r-- | lib/builtins/clear_cache.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/builtins/clear_cache.c b/lib/builtins/clear_cache.c index f92ef1cd4..9dcab344a 100644 --- a/lib/builtins/clear_cache.c +++ b/lib/builtins/clear_cache.c @@ -163,12 +163,14 @@ void __clear_cache(void *start, void *end) { * uintptr_t in case this runs in an IPL32 environment. */ const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15); - for (addr = xstart; addr < xend; addr += dcache_line_size) + for (addr = xstart & ~(dcache_line_size - 1); addr < xend; + addr += dcache_line_size) __asm __volatile("dc cvau, %0" :: "r"(addr)); __asm __volatile("dsb ish"); const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15); - for (addr = xstart; addr < xend; addr += icache_line_size) + for (addr = xstart & ~(icache_line_size - 1); addr < xend; + addr += icache_line_size) __asm __volatile("ic ivau, %0" :: "r"(addr)); __asm __volatile("isb sy"); #elif defined (__powerpc64__) |