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authorHans Wennborg <hans@hanshq.net>2018-01-24 15:56:18 +0000
committerHans Wennborg <hans@hanshq.net>2018-01-24 15:56:18 +0000
commitbd2cfdd1fa03adb7fb366da3842c75016af71101 (patch)
treed84a995134fa2117a1e8766ab6f8ee2a4b39c712
parent8d6a4ba119d0b381698b2e4c3f893dad51b748dc (diff)
Merging r323315:
------------------------------------------------------------------------ r323315 | mstorsjo | 2018-01-24 11:14:52 +0100 (Wed, 24 Jan 2018) | 9 lines [builtins] Align addresses to cache lines in __clear_cache for aarch64 This makes sure that the last cache line gets invalidated properly. This matches the example code at http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/BABJDBHI.html, and also matches what libgcc does. Differential Revision: https://reviews.llvm.org/D42196 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/compiler-rt/branches/release_60@323338 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/builtins/clear_cache.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/builtins/clear_cache.c b/lib/builtins/clear_cache.c
index 881ea9b77..451f1c0b1 100644
--- a/lib/builtins/clear_cache.c
+++ b/lib/builtins/clear_cache.c
@@ -163,12 +163,14 @@ void __clear_cache(void *start, void *end) {
* uintptr_t in case this runs in an IPL32 environment.
*/
const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15);
- for (addr = xstart; addr < xend; addr += dcache_line_size)
+ for (addr = xstart & ~(dcache_line_size - 1); addr < xend;
+ addr += dcache_line_size)
__asm __volatile("dc cvau, %0" :: "r"(addr));
__asm __volatile("dsb ish");
const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15);
- for (addr = xstart; addr < xend; addr += icache_line_size)
+ for (addr = xstart & ~(icache_line_size - 1); addr < xend;
+ addr += icache_line_size)
__asm __volatile("ic ivau, %0" :: "r"(addr));
__asm __volatile("isb sy");
#elif defined (__powerpc64__)