diff options
| author | Coby Tayree <coby.tayree@intel.com> | 2017-12-27 10:01:00 +0000 |
|---|---|---|
| committer | Coby Tayree <coby.tayree@intel.com> | 2017-12-27 10:01:00 +0000 |
| commit | 8b794e9ef26a956e0c720c9daf049cfe23641717 (patch) | |
| tree | 1971b7d01432d27ed66c687bdc3ad2f8c5166df9 /test/Preprocessor | |
| parent | 4086d83a7b37ebaf959bf235ae6ce154fc2d81cb (diff) | |
[x86][icelake][bitalg]
added bitalg feature recognition
added intrinsics support for bitalg instructions
_mm512_popcnt_epi16
_mm512_mask_popcnt_epi16
_mm512_maskz_popcnt_epi16
_mm512_popcnt_epi8
_mm512_mask_popcnt_epi8
_mm512_maskz_popcnt_epi8
_mm512_mask_bitshuffle_epi64_mask
_mm512_bitshuffle_epi64_mask
_mm256_popcnt_epi16
_mm256_mask_popcnt_epi16
_mm256_maskz_popcnt_epi16
_mm128_popcnt_epi16
_mm128_mask_popcnt_epi16
_mm128_maskz_popcnt_epi16
_mm256_popcnt_epi8
_mm256_mask_popcnt_epi8
_mm256_maskz_popcnt_epi8
_mm128_popcnt_epi8
_mm128_mask_popcnt_epi8
_mm128_maskz_popcnt_epi8
_mm256_mask_bitshuffle_epi32_mask
_mm256_bitshuffle_epi32_mask
_mm128_mask_bitshuffle_epi16_mask
_mm128_bitshuffle_epi16_mask
matching a similar work on the backend (D40222)
Differential Revision: https://reviews.llvm.org/D41564
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@321483 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Preprocessor')
| -rw-r--r-- | test/Preprocessor/predefined-arch-macros.c | 2 | ||||
| -rw-r--r-- | test/Preprocessor/x86_target_features.c | 22 |
2 files changed, 24 insertions, 0 deletions
diff --git a/test/Preprocessor/predefined-arch-macros.c b/test/Preprocessor/predefined-arch-macros.c index 2c12e45b9f..dc552c76b5 100644 --- a/test/Preprocessor/predefined-arch-macros.c +++ b/test/Preprocessor/predefined-arch-macros.c @@ -1050,6 +1050,7 @@ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ICL_M32 // CHECK_ICL_M32: #define __AES__ 1 // CHECK_ICL_M32: #define __AVX2__ 1 +// CHECK_ICL_M32: #define __AVX512BITALG__ 1 // CHECK_ICL_M32: #define __AVX512BW__ 1 // CHECK_ICL_M32: #define __AVX512CD__ 1 // CHECK_ICL_M32: #define __AVX512DQ__ 1 @@ -1098,6 +1099,7 @@ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ICL_M64 // CHECK_ICL_M64: #define __AES__ 1 // CHECK_ICL_M64: #define __AVX2__ 1 +// CHECK_ICL_M64: #define __AVX512BITALG__ 1 // CHECK_ICL_M64: #define __AVX512BW__ 1 // CHECK_ICL_M64: #define __AVX512CD__ 1 // CHECK_ICL_M64: #define __AVX512DQ__ 1 diff --git a/test/Preprocessor/x86_target_features.c b/test/Preprocessor/x86_target_features.c index 3581744560..61a57246a5 100644 --- a/test/Preprocessor/x86_target_features.c +++ b/test/Preprocessor/x86_target_features.c @@ -209,11 +209,33 @@ // AVX512VBMI: #define __SSE__ 1 // AVX512VBMI: #define __SSSE3__ 1 +// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512bitalg -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512BITALG %s + +// AVX512BITALG: #define __AVX2__ 1 +// AVX512BITALG: #define __AVX512BITALG__ 1 +// AVX512BITALG: #define __AVX512BW__ 1 +// AVX512BITALG: #define __AVX512F__ 1 +// AVX512BITALG: #define __AVX__ 1 +// AVX512BITALG: #define __SSE2_MATH__ 1 +// AVX512BITALG: #define __SSE2__ 1 +// AVX512BITALG: #define __SSE3__ 1 +// AVX512BITALG: #define __SSE4_1__ 1 +// AVX512BITALG: #define __SSE4_2__ 1 +// AVX512BITALG: #define __SSE_MATH__ 1 +// AVX512BITALG: #define __SSE__ 1 +// AVX512BITALG: #define __SSSE3__ 1 + + // RUN: %clang -target i386-unknown-unknown -march=atom -mavx512vbmi -mno-avx512bw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512VBMINOAVX512BW %s // AVX512VBMINOAVX512BW-NOT: #define __AVX512BW__ 1 // AVX512VBMINOAVX512BW-NOT: #define __AVX512VBMI__ 1 +// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512bitalg -mno-avx512bw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512BITALGNOAVX512BW %s + +// AVX512BITALGNOAVX512BW-NOT: #define __AVX512BITALG__ 1 +// AVX512BITALGNOAVX512BW-NOT: #define __AVX512BW__ 1 + // RUN: %clang -target i386-unknown-unknown -march=atom -msse4.2 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=SSE42POPCNT %s // SSE42POPCNT: #define __POPCNT__ 1 |