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| author | Craig Topper <craig.topper@intel.com> | 2017-12-29 06:39:16 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-12-29 06:39:16 +0000 |
| commit | 6bea6f7d496d5fefec598d69c1e797e2617dce19 (patch) | |
| tree | c7b8efd6c9c475d5fe3a4cb343392878213e8590 /include | |
| parent | ef699b2164acc263ed01dcbe6eb30bc5cab1ad4b (diff) | |
Revert r321504 "[X86] Don't accidentally enable PKU on cannon lake and icelake or CLWB on cannonlake."
I based that commit on what was in Intel's public documentation here https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Which specifically said CLWB wasn't until Icelake.
But I've since cross checked with SDE and it thinks these features exist on CNL and ICL. So now I don't know what to believe.
I've added test coverage of the current behavior as part of the revert so at least now have proof of what we're doing.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@321547 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions