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gdb/ChangeLog:
Update copyright year range in all GDB files
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This is the testsuite for the or1k sim, it tests running many of the
basic architecture instructions on the openrisc sim.
sim/testsuite/sim/or1k/ChangeLog:
2017-12-12 Peter Gavin <pgavin@gmail.com>
Stafford Horne <shorne@gmail.com>
* add.S: New file.
* alltests.exp: New file.
* and.S: New file.
* basic.S: New file.
* div.S: New file.
* ext.S: New file.
* find.S: New file.
* flag.S: New file.
* fpu.S: New file.
* jump.S: New file.
* load.S: New file.
* mac.S: New file.
* mfspr.S: New file.
* mul.S: New file.
* or.S: New file.
* or1k-asm-test-env.h: New file.
* or1k-asm-test-helpers.h: New file.
* or1k-asm-test.h: New file.
* or1k-asm.h: New file.
* or1k-test.ld: New file.
* ror.S: New file.
* shift.S: New file.
* spr-defs.h: New file.
* sub.S: New file.
* xor.S: New file.
sim/testsuite/ChangeLog:
2017-12-12 Stafford Horne <shorne@gmail.com>
Peter Gavin <pgavin@gmail.com>
* configure: Regenerated.
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sim/aarch64/
* simulator.c (vec_load): Add M argument. Rewrite to iterate over
registers based on structure size.
(LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
(LD1_1): Replace with call to vec_load.
(vec_store): Add new M argument. Rewrite to iterate over registers
based on structure size.
(ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
(ST1_1): Replace with call to vec_store.
sim/testsuite/sim/aarch64/
* fcvtz.s, fstur.s, ldn_single.s, ldnr.s, mla.s, mls.s, uzp.s: Align
data.
* sumulh.s: Delete unnecessary data alignment.
* stn_single.s: Align data. Fix unaligned ldr insns. Adjust cmp
arguments to match change.
* ldn_multiple.s, stn_multiple.s: New.
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sim/aarch64/
* simulator.c (do_vec_FCVTL): New.
(do_vec_op1): Call do_vec_FCVTL.
sim/testsuite/sim/aarch64/
* fcvtl.s: New.
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sim/aarch64/
* simulator.c (do_scalar_FCMGE_zero): New.
(do_scalar_FCMLE_zero, do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero)
(do_scalar_FCMLT_zero): Likewise.
(do_scalar_vec): Add calls to new functions.
sim/testsuite/sim/aarch64/
* fcmXX.s: New.
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sim/aarch64/
* simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
flag check.
sim/testsuite/sim/aarch64/
* adds.s: Add checks for values -2 and 1, where C is not set.
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sim/aarch64/
* simulator.c (mul64hi): Shift carry left by 32.
(smulh): Change signum to negate. If negate, invert result, and add
carry bit if low part of multiply result is zero.
sim/testsuite/sim/aarch64/
* sumov.s: Correct compare test values.
* sumulh.s: New.
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sim/aarch64/
* simulator.c (do_vec_SMOV_into_scalar): New.
(do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
Rewritten.
(do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
(do_vec_op1): Move do_vec_TRN call and do_vec_UZP call. Add
do_vec_SMOV_into_scalar call. Delete do_vec_MOV_into_scalar and
do_vec_UMOV calls. Add do_vec_UMOV_into_scalar call.
sim/testsuite/sim/aarch64/
* sumov.s: New.
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sim/aarch64/
* simulator.c (popcount): New.
(do_vec_CNT): New.
(do_vec_op1): Add do_vec_CNT call.
sim/testsuite/sim/aarch64/
* cnt.s: New.
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sim/aarch64/
* simulator.c (do_vec_ADDV): Mov val declaration inside each case,
with type set to input type size.
(do_vec_xtl): Change bias from 3 to 4 for byte case.
sim/testsuite/sim/aarch64/
* bit.s: Change cmp immediates to account for addv bug fix.
* cmtst.s, ldn_single.s, stn_single.s: Likewise.
* xtl.s: New.
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sim/
* MAINTAINTERS (aarch64): Add myself.
sim/aarch64/
* simulator.c (do_vec_MLA): Rewrite switch body.
sim/testsuite/sim/aarch64/
* mla.s: New.
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sim/aarch64/
* simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
2. Move test_false if inside loop. Fix logic for computing result
stored to vd.
sim/testsuite/sim/aarch64
* bit.s: New.
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sim/aarch64/
* simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
(do_vec_LDn_single, do_vec_STn_single): New.
(do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with
loop over nregs using new var n. Add n times size to address in loop.
Add n to vd in loop.
(do_vec_load_store): Add comment for instruction bit 24. New var
single to hold instruction bit 24. Add new code to use single. Move
ldnr support inside single if statements. Fix ldnr register counts
inside post if statement. Change HALT_NYI calls to HALT_UNALLOC.
sim/testsuite/sim/aarch64/
* ldn_single.s: New.
* ldnr.s: New.
* stn_single.s: New.
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sim/aarch64/
* simulator.c (do_vec_compare): Add case 0x23 for CMTST.
sim/testsuite/sim/aarch64/
* cmtst.s: New.
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sim/aarch64/
* simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In
case 3, call HALT_UNALLOC unconditionally.
(do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to
i + 2. Delete if on bias, change index to i + bias * X.
sim/testsuite/sim/aarch64/
* addv.s: New.
* xtn.s: New.
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sim/aarch64/
* simulator.c (do_vec_UZP): Rewrite.
sim/testsuite/sim/aarch64/
* uzp.s: New.
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sim/aarch64/
* cpustate.c: Include math.h.
(aarch64_set_FP_float): Use signbit to check for signed zero.
(aarch64_set_FP_double): Likewise.
* simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
(do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
args same size as third arg.
(fmaxnm): Use isnan instead of fpclassify.
(fminnm, dmaxnm, dminnm): Likewise.
(do_vec_MLS): Reverse order of subtraction operands.
(dexSimpleFPCondSelect): Call aarch64_get_FP_double or
aarch64_get_FP_float to get source register contents.
(UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
(do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
raise_exception calls.
sim/testsuite/sim/aarch64/
* fcsel.s: New.
* fcvtz.s: New.
* fminnm.s: New.
* mls.s: New.
* mul.s: New.
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This applies the second part of GDB's End of Year Procedure, which
updates the copyright year range in all of GDB's files.
gdb/ChangeLog:
Update copyright year range in all GDB files.
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sim/aarch64/
* simulator.c (set_flags_for_float_compare): Add code to handle Inf.
Add comment to document NaN issue.
(set_flags_for_double_compare): Likewise.
sim/testsuite/sim/aarch64/
* fcmp.s: New.
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sim/aarch64
* simulator.c (NEG, POS): Move before set_flags_for_add64.
(set_flags_for_add64): Replace with a modified copy of
set_flags_for_sub64.
sim/testsuite/sim/aarch64
* testutils.inc (pass): Move .Lpass to start.
(fail): Move .Lfail to start. Return 1 instead of 0.
(start): Moved .Lpass and .Lfail to here.
* adds.s: New.
* fstur.s: New.
* tbnz.s: New.
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No other sub directory provides such a configuration option, so
drop it from the sim dir as well. This cleans up a good bit of
code in the process.
If people want to use custom flags for just the sim, they can
still run configure+make by hand in the sim subdir and use the
normal CFLAGS settings.
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sim/testsuite/sim/mips/ChangeLog:
* hilo-hazard-4.s: Change copyright ownder to FSF.
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ld * emulparams/msp430elf.sh (RAM_START): Move to 0x500 - above the
MSP430 hardware multiply address range.
* scripttempl/elf32msp430.sc (__romdatastart): Define.
(__romdatacopysize): Define.
* scripttempl/elf32msp430_3.sc: Likewise.
tests * testutils.inc (__pass): Use the LMA addresses of the _passmsg
symbol.
(__fail): Likewise.
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The cris sim hit a few failures after the recent getopt logic, and the
expected output showed a few ways we can improve things to better match
other utils.
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Rather than re-invent endian defines, as well as maintain our own list
of OS & arch-specific includes, punt all that logic in favor of the bfd
ones already set up and maintained elsewhere. We already rely on the
bfd library, so leveraging the endian aspect should be fine.
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gdb/ChangeLog:
Update year range in copyright notice of all files.
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The cris port was using the device framework to handle two addresses when
the --cris-900000xx flag was specified. That can be implemented using the
newer hardware framework instead which allows us to drop the device logic
entirely, as well as delete the tconfig.h file. Basically we create a new
cris_900000xx device model and move the read logic out of devices.c and
into that. The rest of the devices logic was callback to the hardware
framework already.
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Much like we autodetect the path to the run program when there is none
set explicitly, do the same for the rvdummy program. Otherwise the
default make check fails to execute the helper properly.
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Most targets already default to loading code via their LMA, but for
a few, this means the default changes from loading VMA to LMA. It's
better to have the different targets be consistent, and allows some
code clean up.
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sim * configure.tgt: Add aarch64 entry.
* configure: Regenerate.
* sim/aarch64/configure.ac: New configure template.
* sim/aarch64/aclocal.m4: Generate.
* sim/aarch64/config.in: Generate.
* sim/aarch64/configure: Generate.
* sim/aarch64/cpustate.c: New file - functions for accessing
AArch64 registers.
* sim/aarch64/cpustate.h: New header.
* sim/aarch64/decode.h: New header.
* sim/aarch64/interp.c: New file - interface between GDB and
simulator.
* sim/aarch64/Makefile.in: New makefile template.
* sim/aarch64/memory.c: New file - functions for simulating
aarch64 memory accesses.
* sim/aarch64/memory.h: New header.
* sim/aarch64/sim-main.h: New header.
* sim/aarch64/simulator.c: New file - aarch64 simulator
functions.
* sim/aarch64/simulator.h: New header.
include/gdb * sim-aarch64.h: New file.
sim/test * configure: Regenerate.
* sim/aarch64: New directory.
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Sometimes in tests, we need supplemental files like linker scripts or
board helper files. There's no way to set those flags in the tests
currently and relative paths don't work (breaks out of tree builds).
Update the main option parser to replace some strings on the fly. Now
tests can do things like:
Long term we'll want to switch the framework to use the dejagnu helpers
like dg-xxx that gcc & gdb utilize. But that'll require more rework.
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Various target code belongs in the testsuite/ subdir, so move the m32c
code to match all the other targets.
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Adds test coverage for recent features.
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When handling left saturated ashifts with negative immediates, they
should be treated as right ashifts. This matches hardware behavior.
Reported-by: Igor Rayak <igorr@gitatechnologies.com>
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2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
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sim/testsuite:
* sim-defs.exp (sim_init): Unset target ldscript here.
sim/testsuite/sim/mips:
* basic.exp: Don't unset target ldscript here.
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The nrun conversion was slightly incorrect in how it stopped when an
exception occurred. We still set cpu.asregs.exception, but nothing
was checking it anymore. Convert all of that to sim_engine_halt.
To keep things from regressing again, add a basic testsuite too.
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A lot of cpu state is stored in global variables, as is memory handling.
The sim_size support needs unwinding at some point. But at least this
is an improvement on the status quo.
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Looks like historical restructuring in this dir lost the d10v-elf subdir
and no one noticed in the meantime. Re-add it to the testsuite.
There are some failures, but better some tests get run than none at all.
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The current cr16 testsuite sets up _START, but the linker looks for the
_start symbol. Add the latter as an alias to the former.
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Since the sim doesn't have any debug support in it, we can only exit
cleanly. But this is still better than nothing.
Change the default microblaze sim to not dump the debug load output
when running. No other does this, and it breaks the testsuite.
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If a test doesn't write anything at all to stdout, the current test
framework can't support that. Even if you put a blank output line:
# output:
the setup happily clobbers that with a default pass/fail string.
Tweak the parsing logic so we only set the output to pass/fail when
the test has no output marker.
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Since the testsuite subdir has to handle dynamic arch values already,
there's no real value in requiring arches to opt in to it. Most have
a testsuite now anyways, and we're requiring it in the future.
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