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binutils-2_31_1-amp-branch
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Binutils/GDB including Ampere Computing toolchain specific patches
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opcodes
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Author
2017-11-03
[ARC] Sync opcode data base.
claziss
2017-10-25
PR22348, conflicting global vars in crx and cr16
Alan Modra
2017-10-24
RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0
Andrew Waterman
2017-10-23
Add missing ChangeLog entries
Igor Tsimbalist
2017-10-23
Fix the master due to bad regenerated files
Igor Tsimbalist
2017-10-23
Enable Intel AVX512_BITALG instructions.
Igor Tsimbalist
2017-10-23
Enable Intel AVX512_VNNI instructions.
Igor Tsimbalist
2017-10-23
Enable Intel VPCLMULQDQ instruction.
Igor Tsimbalist
2017-10-23
Enable Intel VAES instructions.
Igor Tsimbalist
2017-10-23
Enable Intel GFNI instructions.
Igor Tsimbalist
2017-10-23
Enable Intel AVX512_VBMI2 instructions.
Igor Tsimbalist
2017-10-18
[Visium] Disassemble the operands of the stop instruction.
Eric Botcazou
2017-10-12
FT32: support for FT32B processor - part 1
James Bowman
2017-10-09
S/390: Sync with latest POP - 3 new instructions
Andreas Krebbel
2017-10-09
S/390: Sync with IBM z14 POP - SI_RD format
Andreas Krebbel
2017-10-01
Add new mnemonics for VLE multiple load instructions
Alexander Fedotov
2017-09-27
Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions,...
Nick Clifton
2017-09-26
Allow the macw and macl instructions to be used on CPUs that have emacs support.
Nick Clifton
2017-09-25
Initialize 'imm' on opcodes/aarch64-opc.c:expand_fp_imm (and fix breakage on ...
Sergio Durigan Junior
2017-09-11
nds32: Rename __BIT() to N32_BIT().
Kuan-Lin Chen
2017-09-09
x86: Remove restriction on NOTRACK prefix position
H.J. Lu
2017-08-31
Add updated French translations for opcodes and gprof
Nick Clifton
2017-08-30
FT32: improve disassembly readability
James Bowman
2017-08-24
[PowerPC VLE] Add SPE2 and EFS2 instructions support
Alexander Fedotov
2017-08-23
ppc-opc.c formatting
Alan Modra
2017-08-22
RISC-V: Mark "c.nop" as an alias
Palmer Dabbelt
2017-08-21
[PowerPC VLE] Add LSP (Lightweight Signal Processing) instruction support
Alexander Fedotov
2017-08-09
[ARM] Don't warn on REG_SP when used in CRC32 instructions
Jiong Wang
2017-08-07
Mark big and mach with ATTRIBUTE_UNUSED
H.J. Lu
2017-08-07
GDB/opcodes: Remove arch/mach/endian disassembler assertions
Maciej W. Rozycki
2017-07-25
Fix typos in error and option messages in OPCODES library.
Nick Clifton
2017-07-24
[AArch64] Fix the bit pattern order in the comments in auto-generated file
Jiong Wang
2017-07-21
S/390: Support z14 as CPU name.
Andreas Krebbel
2017-07-20
Update the German translation for the opcodes library.
Nick Clifton
2017-07-19
[ARC] Add SecureShield AUX registers
claziss
2017-07-19
[ARC] Add SJLI instruction.
Claudiu Zissulescu
2017-07-19
[ARC] Add JLI support.
John Eric Martin
2017-07-18
Fix spelling typos.
Yuri Chornovian
2017-07-14
binutils/objdump: Fix disassemble for huge elf sections
Ravi Bangoria
2017-07-12
Update PO files
Alan Modra
2017-07-11
Mark generated cgen files read-only
Alan Modra
2017-07-07
Move print_insn_XXX to an opcodes internal header, again
Alan Modra
2017-07-05
X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctly
Borislav Petkov
2017-07-05
Fixup changelog entries for previous commit
Ramana Radhakrishnan
2017-07-04
[Patch ARM] Support MVFR2 VFP Coprocessor register for ARMv8-A
Ramana Radhakrishnan
2017-07-04
Regenerate configure.
Tristan Gingold
2017-07-03
Regenerate pot files.
Tristan Gingold
2017-06-30
MIPS/opcodes: Reorder LSA and DLSA instructions
Maciej W. Rozycki
2017-06-30
MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support (ChangeLog)
Maciej W. Rozycki
2017-06-30
MIPS: Add microMIPS XPA support
Maciej W. Rozycki
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