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path: root/include/opcode
AgeCommit message (Expand)Author
2017-03-21S/390: Remove vx2 facility flagAndreas Krebbel
2017-03-21arc/nps400: Add cp16/cp32 instructions to opcodes libraryRinat Zelig
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford
2017-02-24[AArch64] Add a "compnum" featureRichard Sandiford
2017-02-24Add new counter-enable CSRsAndrew Waterman
2017-02-23S/390: Add support for new cpu architecture - arch12.Andreas Krebbel
2017-02-23opcodes,gas: associate SPARC ASIs with an architecture level.Sheldon Lobo
2017-02-15Add SFENCE.VMA instructionAndrew Waterman
2017-02-14PowerPC register expression checksAlan Modra
2017-02-06[ARC] Provide an interface to decode ARC instructions.Claudiu Zissulescu
2017-01-25Clarify that include/opcode/ files are part of GNU opcodesDimitar Dimitrov
2017-01-04[AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy
2017-01-03Add support for the Q extension to the RISCV ISA.Kito Cheng
2017-01-02Update year range in copyright notice of all files.Alan Modra
2016-12-31PRU BFD supportDimitar Dimitrov
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki
2016-12-23MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki
2016-12-21Remove high bit set charactersAlan Modra
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li
2016-12-09MIPS16: Remove unused `>' operand codeMaciej W. Rozycki
2016-12-07MIPS/include: opcode/mips.h: Correct INSN_CHIP_MASKMaciej W. Rozycki
2016-12-07MIPS/include: opcode/mips.h: Add a comment for ASE_DSPR3Maciej W. Rozycki
2016-12-05[ARM] Add ARMv8.3 command line option and feature flagSzabolcs Nagy
2016-11-29[ARC] Add checking for LP_COUNT reg usage, improve error reporting.Claudiu Zissulescu
2016-11-22gas,opcodes: fix hardware capabilities bumping in the sparc assembler.Jose E. Marchesi
2016-11-22PR20744, Incorrect PowerPC VLE relocsAlan Modra
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy
2016-11-11[AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy
2016-11-11[AArch64] Add ARMv8.3 command line option and feature flagSzabolcs Nagy
2016-11-04Add support for ARM Cortex-M33 processorThomas Preud'homme
2016-11-03arc: Implement NPS-400 dcmac instructionGraham Markall
2016-11-03arc: Change max instruction length to 64-bitsAndrew Burgess
2016-11-03opcodes/arc: Make some macros 64-bit safeGraham Markall
2016-11-03arc: Replace ARC_SHORT macro with arc_opcode_len functionGraham Markall
2016-11-01Add support for RISC-V architecture.Nick Clifton
2016-10-14[ARC] Disassembler: fix LIMM detection for short instructions.Claudiu Zissulescu
2016-09-29Disallow 3-operand cmp[l][i] for ppc64Alan Modra
2016-09-26[ARC] ISA alignment.Claudiu Zissulescu
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford
2016-09-21[AArch64][SVE 30/32] Add SVE instruction classesRichard Sandiford
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford
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