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2017-11-23Fix build error with --enable-targets=all.Jim Wilson
gas/ * as.c (INITIALIZING_EMULS): Define. * config/obj-multi.h (FAKE_LABEL_NAME): When INITIALIZING_EMULS set, don't define it.
2017-11-23Add Disp8MemShift for AVX512 VAES instructions.Igor Tsimbalist
opcodes/ * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions. * i386-tbl.h: Regenerate. gas/ * testsuite/gas/i386/avx512f_vaes-intel.d: Regenerate. * testsuite/gas/i386/avx512f_vaes.d: Likewise. * testsuite/gas/i386/avx512f_vaes-wig1-intel.d: Likewise. * testsuite/gas/i386/avx512f_vaes-wig1.d: Likewise. * testsuite/gas/i386/avx512vl_vaes-intel.d: Likewise. * testsuite/gas/i386/avx512vl_vaes.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_vaes.s: Add instructions with disp8*N. * testsuite/gas/i386/x86-64-avx512f_vaes-intel.d: Regenerate. * testsuite/gas/i386/x86-64-avx512f_vaes.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_vaes-wig.s: Add instructions with disp8*N. * testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d: Regenerate. * testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d: Regenerate. * testsuite/gas/i386/x86-64-avx512vl_vaes.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s: Add instructions with disp8*N. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d: Regenerate. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d: Regenerate.
2017-11-23x86: fix AVX-512 16-bit addressingJan Beulich
Despite EVEX encodings not being available in real and VM86 modes, 16-bit addressing still needs to be handled properly for 16-bit protected mode as well as 16-bit addressing in 32-bit mode. Neither should displacements be dropped silently by the assembler, nor should the disassembler fail to correctly scale 8-bit displacements.
2017-11-23x86-64: always use unsigned 32-bit reloc for 32-bit addressing w/o base regJan Beulich
Except for %eip-relative addressing, where we don't have a suitable relocation type silently wrapping at the 4G boundary, consistently force use of R_X86_64_32 (in ELF terms) instead of its sign-extending counterpart. This wasn't right in case there was no base register in the addressing expression.
2017-11-23x86: drop redundant VSIB handling codeJan Beulich
The vecsib && !base_reg case is already being handled (in a more correct manner) by earlier code.
2017-11-23x86: correct UDnJan Beulich
Make the assembler recognize UD0, supporting only the newer form expecting a ModR/M byte. Make assembler and disassembler properly emit / expect a ModR/M byte for UD1. For the testsuite, as arch-4 already tests all UDn, avoid producing a huge delta for other tests using UD2B by making them use UD2 instead.
2017-11-23x86/Intel: don't report multiple errors for a single insn operandJan Beulich
Multiple errors are more confusing than helpful, as the more generic one often implies a sufficiently different adjustment than would actually be needed to fix the code. Additionally it makes it more cumbersome to add missing error checks, as the testsuite then needs extra updating.
2017-11-22Riscv ld-elf/stab failure and fake label cleanup.Jim Wilson
* as.c: Include write.h. (common_emul_init): Use FAKE_LABEL_NAME. * ecoff.c (add_file, ecoff_directive_end, ecoff_directive_loc): Likewise. (ecoff_build_symbols): Use FAKE_LABEL_CHAR. * expr.c (get_symbol_name): Use FAKE_LABEL_CHAR. Accept only if input_from_string is TRUE. * read.c (input_from_string): New. (read_symbol_name): Use FAKE_LABEL_CHAR. Accept only if input_from_string is TRUE. (temp_ilp): Set input_from_string to TRUE. (restore_ilp): Set input_from_string to FALSE. * read.h (input_from_string): Declare. * symbols.c: Include write.h (S_IS_LOCAL): Check for FAKE_LABEL_CHAR. (symbol_relc_make_sym): Fix comment refering to default fake label string. * write.h (FAKE_LABEL_CHAR): New. * config/tc-riscv.h (FAKE_LABEL_CHAR): Define. * testsuite/gas/all/err-fakelabel.s: New.
2017-11-22Update docs on filling text with nops.Jim Wilson
gas/ * doc/as.texinfo (.align): Change some to most for text nop fill. (.balign, .p2align): Likewise.
2017-11-22[GAS/ARM] Clarify relation between reg_expected_msgs and arm_reg_typeThomas Preud'homme
Uses of reg_expected_msgs rely on each arm_reg_type enumerator to have a message entry in the same order as the enumerator declaration. This is not clearly stated in the definition of both the arm_reg_type enum and the reg_expected_msgs. Worse, there is nothing to ensure both are kept in sync. As an attempt towards this, this patch uses C99 array designators to ensure that each message is associated with the right arm_reg_type. A comment is also added near the definition of arm_reg_type to point to the reg_expected_msgs array. Finally, the array is synced with arm_reg_type by adding the missing error message for REG_TYPE_RNB. 2017-11-22 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_reg_type): Comment on the link with reg_expected_msgs. (reg_expected_msgs): Initialize using array designators with arm_reg_type index.
2017-11-22[ARC] Fix handling of ARCv2 H-register class.claziss
For ARCv2, h-regs are only valid unitl r31. gas/ 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/hregs-err.s: New test. opcodes/ 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (insert_rhv2): Check h-regs range.
2017-11-21x86: Add tests for -n option of x86 assemblerH.J. Lu
The -n command-line of x86 assembler disables optimization of alignment directives, like ".balign 8, 0x90", with multi-byte nop instructions such as leal 0(%esi),%esi. PR gas/22464 * testsuite/gas/i386/align-1.s: New file. * testsuite/gas/i386/align-1a.d: Likewise. * testsuite/gas/i386/align-1b.d: Likewise. * testsuite/gas/i386/i386.exp: Run align-1a and align-1b.
2017-11-21[ARC] Improve printing of pc-relative instructions.claziss
opcodes/ 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets. * arc-opc.c (SIMM21_A16_5): Make it pc-relative. gas/ 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/b.d : Update test. * testsuite/gas/arc/bl.d: Likewise. * testsuite/gas/arc/jli-1.d: Likewise. * testsuite/gas/arc/lp.d: Likewise. * testsuite/gas/arc/pcl-relocs.d: Likewise. * testsuite/gas/arc/pcrel-relocs.d: Likewise. * testsuite/gas/arc/pic-relocs.d: Likewise. * testsuite/gas/arc/plt-relocs.d: Likewise. * testsuite/gas/arc/pseudos.d: Likewise. * testsuite/gas/arc/relax-avoid2.d: Likewise. * testsuite/gas/arc/relax-avoid3.d: Likewise. * testsuite/gas/arc/relax-b.d: Likewise. * testsuite/gas/arc/tls-relocs.d: Likewise. * testsuite/gas/arc/relax-add01.d: Likewise. * testsuite/gas/arc/relax-add04.d: Likewise. * testsuite/gas/arc/relax-ld01.d: Likewise. * testsuite/gas/arc/relax-sub01.d: Likewise. * testsuite/gas/arc/relax-sub02.d: Likewise. * testsuite/gas/arc/relax-sub04.d: Likewise. * testsuite/gas/arc/pcl-print.s: New file. * testsuite/gas/arc/pcl-print.d: Likewise. * testsuite/gas/arc/nps400-12.d: Likewise. ld/ 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/ld-arc/jli-simple.d: Update test.
2017-11-21xtensa error messageAlan Modra
* config/tc-xtensa.c (finish_vinsn): Avoid multiple ngettext calls in error message.
2017-11-21mingw gas testsuite fixAlan Modra
Some x86_64 targets pad sections with nops. * testsuite/gas/i386/x86-64-reg-bad.l: Accept trailing padding.
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina
This patch separates the new FP16 instructions backported from Armv8.4-a to Armv8.2-a into a new flag order to distinguish them from the rest of the already existing optional FP16 instructions in Armv8.2-a. The new flag "+fp16fml" is available from Armv8.2-a and implies +fp16 and is mandatory on Armv8.4-a. gas/ * config/tc-aarch64.c (fp16fml): New. * doc/c-aarch64.texi (fp16fml): New. * testsuite/gas/aarch64/armv8_2-a-crypto-fp16.d (fp16): Make fp16fml. * testsuite/gas/aarch64/armv8_3-a-crypto-fp16.d (fp16): Make fp16fml. include/ * opcode/aarch64.h: (AARCH64_FEATURE_F16_FML): New. (AARCH64_ARCH_V8_4): Enable AARCH64_FEATURE_F16_FML by default. opcodes/ * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML and AARCH64_FEATURE_F16.
2017-11-16Correct AArch64 crypto dependencies.Tamar Christina
The crypto options depend on SIMD and FP, the documentation states so but the dependency is not there the code. We have mostly gotten away with this due to the default flags for the architectures (e.g. Armv8.2-a implies +simd) but this discrepancy needs to be addressed. gas/ 2017-11-16 Tamar Christina <tamar.christina@arm.com> * opcodes/aarch64-tbl.h (aarch64_feature_crypto): Add ARCH64_FEATURE_SIMD and AARCH64_FEATURE_FP. (aarch64_feature_crypto_v8_2, aarch64_feature_sm4): Likewise. (aarch64_feature_sha3): Likewise.
2017-11-16Update documentation for Arvm8.4-A changes to AArch64.Tamar Christina
gas/ 2017-11-16 Tamar Christina <tamar.christina@arm.com> * doc/c-aarch64.texi (armv8.4-a, sha2, sha3, sm4): New. (dotprod): Update default note.
2017-11-16Add assembler and disassembler support for the new Armv8.4-a instructions ↵Tamar Christina
for AArch64. Some of these instructions have been back-ported as optional extensions to Armv8.2-a and higher, but others are only available for Armv8.4-a. opcodes/ * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New. (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New. (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New. (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New. (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New. (ldapur, ldapursw, stlur): New. * aarch64-dis-2.c: Regenerate. gas/ * testsuite/gas/aarch64/armv8_4-a-illegal.d: New. * testsuite/gas/aarch64/armv8_4-a-illegal.l: New. * testsuite/gas/aarch64/armv8_4-a-illegal.s: New. * testsuite/gas/aarch64/armv8_4-a.d: New. * testsuite/gas/aarch64/armv8_4-a.s: New. * testsuite/gas/aarch64/armv8_2-a-crypto-fp16.s: New. * testsuite/gas/aarch64/armv8_2-a-crypto-fp16.d: New. * testsuite/gas/aarch64/armv8_3-a-crypto-fp16.d: New. * testsuite/gas/aarch64/armv8_4-a-crypto-fp16.d: New. * testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.s: New. * testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.l: New. * testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.d: New.
2017-11-16x86: ignore high register select bit(s) in 32- and 16-bit modesJan Beulich
While commits 9889cbb14e ("Check invalid mask registers") and abfcb414b9 ("X86: Ignore REX_B bit for 32-bit XOP instructions") went a bit into the right direction, this wasn't quite enough: - VEX.vvvv has its high bit ignored - EVEX.vvvv has its high bit ignored together with EVEX.v' - the high bits of {,E}VEX.vvvv should not be prematurely zapped, to allow proper checking of them when the fields has to hold al ones - when the high bits of an immediate specify a register, bit 7 is ignored
2017-11-16ix86/Intel: don't require memory operand size specifier for PTWRITEJan Beulich
Other than in 64-bit mode, in 32- and 16-bit modes operand size isn't ambiguous.
2017-11-16i386: Replace .code64/.code32 with .byteH.J. Lu
Since .code64 directive isn't available for 32-bit BFD and ELF directive isn't available for non-ELF directive, we should avoid them. * testsuite/gas/i386/noextreg.s: Replace .code64/.code32 and 64-bit instructions with .byte. Remove ELF directive.
2017-11-15Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a ↵Tamar Christina
into a new flag order to distinguish them from the rest of the already existing optional FP16 instructions in Armv8.2-a. The new flag "+fp16fml" is available from Armv8.2-a and implies +fp16 and is mandatory from Armv8.4-a. gas/ * config/tc-arm.c (arm_ext_fp16_fml, fp16fml): New. (do_neon_fmac_maybe_scalar_long): Use arm_ext_fp16_fml. * doc/c-arm.texi (fp16, fp16fml): New. * testsuite/gas/arm/armv8_2-a-fp16.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_3-a-fp16.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_2-a-fp16-illegal.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_2-a-fp16-thumb2.d (fp16): Make fp16fml. include/ * opcode/arm.h: (ARM_EXT2_FP16_FML): New. (ARM_AEXT2_V8_4A): Add ARM_EXT2_FP16_FML.
2017-11-15Add support to readelf and objdump for following links to separate debug ↵Nick Clifton
information files. Hi Guys, I am applying the rather large patch attached to this email to enhance the readelf and objdump programs so that they now have the ability to follow links to separate debug info files. (As requested by PR 15152). So for example whereas before we had this output: $ readelf -wi main.exe Contents of the .debug_info section: [...] <15> DW_AT_comp_dir : (alt indirect string, offset: 0x30c) [...] With the new option enabled we get: $ readelf -wiK main.exe main.exe: Found separate debug info file: dwz.debug Contents of the .debug_info section (loaded from main.exe): [...] <15> DW_AT_comp_dir : (alt indirect string, offset: 0x30c) /home/nickc/Downloads/dwzm [...] The link following feature also means that we can get two lots of output if the same section exists in both the main file and the separate debug info file: $ readelf -wiK main.exe main.exe: Found separate debug info file: dwz.debug Contents of the .debug_info section (loaded from main.exe): [...] Contents of the .debug_info section (loaded from dwz.debug): [...] The patch also adds the ability to display the contents of debuglink sections: $ readelf -wk main.exe Contents of the .gnu_debugaltlink section: Separate debug info file: dwz.debug Build-ID (0x14 bytes): c4 a8 89 8d 64 cf 70 8a 35 68 21 f2 ed 24 45 3e 18 7a 7a 93 Naturally there are long versions of these options (=follow-links and =links). The documentation has been updated as well, and since both readelf and objdump use the same set of debug display options, I have moved the text into a separate file. There are also a couple of new binutils tests to exercise the new behaviour. There are a couple of missing features in the current patch however, although I do intend to address them in follow up submissions: Firstly the code does not check the build-id inside separate debug info files when it is searching for a file specified by a .gnu_debugaltlink section. It just assumes that if the file is there, then it contains the information being sought. Secondly I have not checked the DWARF-5 version of these link features, so there will probably be code to add there. Thirdly I have only implemented link following for the DW_FORM_GNU_strp_alt format. Other alternate formats (eg DW_FORM_GNU_ref_alt) have yet to be implemented. Lastly, whilst implementing this feature I found it necessary to move some of the global variables used by readelf (eg section_headers) into a structure that can be passed around. I have moved all of the global variables that were necessary to get the patch working, but I need to complete the operation and move the remaining, file-specific variables (eg dynamic_strings). Cheers Nick binutils PR 15152 * dwarf.h (enum dwarf_section_display_enum): Add gnu_debuglink, gnu_debugaltlink and separate_debug_str. (struct dwarf_section): Add filename field. Add prototypes for load_separate_debug_file, close_debug_file and open_debug_file. * dwarf.c (do_debug_links): New. (do_follow_links): New. (separate_debug_file, separate_debug_filename): New. (fetch_alt_indirect_string): New function. Retrieves a string from the debug string table in the separate debug info file. (read_and_display_attr_value): Use it with DW_FORM_GNU_strp_alt. (load_debug_section_with_follow): New function. Like load_debug_section, but if the first attempt fails, then tries again in the separate debug info file. (introduce): New function. (process_debug_info): Use load_debug_section_with_follow and introduce. (load_debug_info): Likewise. (display_debug_lines_raw): Likewise. (display_debug_lines_decoded): Likewise. (display_debug_macinfo): Likewise. (display_debug_macro): Likewise. (display_debug_abbrev): Likewise. (display_debug_loc): Likewise. (display_debug_str): Likewise. (display_debug_aranges): Likewise. (display_debug_addr); Likewise. (display_debug_frames): Likewise. (display_gdb_index): Likewise. (process_cu_tu_index): Likewise. (load_cu_tu_indexes): Likewise. (display_debug_links): New function. Displays the contents of a .gnu_debuglink or .gnu_debugaltlink section. (calc_gnu_debuglink_ctc32):New function. Calculates a CRC32 value. (check_gnu_debuglink): New function. Checks the CRC of a potential separate debug info file. (parse_gnu_debuglink): New function. Reads a CRC value out of a .gnu_debuglink section. (check_gnu_debugaltlink): New function. (parse_gnu_debugaltlink): New function. Reads the build-id value out of a .gnu_debugaltlink section. (load_separate_debug_info): New function. Finds and loads a separate debug info file. (load_separate_debug_file): New function. Attempts to find and follow a link to a separate debug info file. (free_debug_memory): Free the separate debug info file information. (opts_table): Add "follow-links" and "links". (dwarf_select_sections_by_letters): Add "k" and "K". (debug_displays): Reformat. Add .gnu-debuglink and .gnu_debugaltlink. Add an extra entry for .debug_str in a separate debug info file. * doc/binutils.texi: Move description of debug dump features common to both readelf and objdump into... * objdump.c (usage): Add -Wk and -WK. (load_specific_debug_section): Initialise the filename field in the dwarf_section structure. (close_debug_file): New function. (open_debug_file): New function. (dump_dwarf): Load and dump the separate debug info sections. * readelf.c (struct filedata): New structure. Contains various variables that used to be global: (current_file_size, string_table, string_table_length, elf_header) (section_headers, program_headers, dump_sects, num_dump_sects): Move into filedata structure. (cmdline): New global variable. Contains list of sections to dump by number, as specified on the command line. Add filedata parameter to most functions. (load_debug_section): Load the string table if it has not already been retrieved. (close_file): New function. (close_debug_file): New function. (open_file): New function. (open_debug_file): New function. (process_object): Process sections in any separate debug info files. * doc/debug.options.texi: New file. Add description of =links and =follow-links options. * NEWS: Mention the new feature. * elfcomm.c: Have the byte gte functions take a const pointer. * elfcomm.h: Update prototypes. * testsuite/binutils-all/dw5.W: Update expected output. * testsuite/binutils-all/objdump.WL: Update expected output. * testsuite/binutils-all/objdump.exp: Add test of -WK and -Wk. * testsuite/binutils-all/readelf.exp: Add test of -wK and -wk. * testsuite/binutils-all/readelf.k: New file. * testsuite/binutils-all/objdump.Wk: New file. * testsuite/binutils-all/objdump.WK2: New file. * testsuite/binutils-all/linkdebug.s: New file. * testsuite/binutils-all/debuglink.s: New file. gas * testsuite/gas/avr/large-debug-line-table.d: Update expected output. * testsuite/gas/elf/dwarf2-11.d: Likewise. * testsuite/gas/elf/dwarf2-12.d: Likewise. * testsuite/gas/elf/dwarf2-13.d: Likewise. * testsuite/gas/elf/dwarf2-14.d: Likewise. * testsuite/gas/elf/dwarf2-15.d: Likewise. * testsuite/gas/elf/dwarf2-16.d: Likewise. * testsuite/gas/elf/dwarf2-17.d: Likewise. * testsuite/gas/elf/dwarf2-18.d: Likewise. * testsuite/gas/elf/dwarf2-5.d: Likewise. * testsuite/gas/elf/dwarf2-6.d: Likewise. * testsuite/gas/elf/dwarf2-7.d: Likewise. ld * testsuite/ld-avr/gc-section-debugline.d: Update expected output.
2017-11-15x86: use correct register namesJan Beulich
VEX.W may be legitimately set (and is then ignored by the CPU) for non-64-bit code. Don't print 64-bit register names in such a case, by utilizing that REX_W would never be set for non-64-bit code, and that it is being set from VEX.W by generic decoding. A test for this is going to be introduced in the next patch of this series.
2017-11-15x86: drop VEXI4_Fixup()Jan Beulich
The low four bits of an immediate being set when the high bits specify a fourth register operand is not a problem: CPUs ignore these bits rather than raising #UD. Take care of incrementing codep in OP_EX_VexW() instead.
2017-11-15x86-64: don't allow use of %axl as accumulatorJan Beulich
Just like %cxl can't be used as shift count register. Otherwise for consistency %cxl would need to gain "ShiftCount" and use of both ought to properly cause REX prefixes to be emitted.
2017-11-14First part of fix for riscv gas lns-common-1 failure.Jim Wilson
gas/ * testsuite/gas/lns/lns.exp (lns-common-1): Add riscv*-*-* to alt list.
2017-11-14x86: add disassembler support for XOP VPCOM* pseudo-opsJan Beulich
Matching up with the assembler, which already supports them.
2017-11-14x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich
... matching up with VPCMP*{D,Q}.
2017-11-14x86: string insns don't allow displacementsJan Beulich
Remove the misleading indicators from the table.
2017-11-13gas/arm64: don't emit stack pointer symbol table entriesJan Beulich
Without this change, all of mov z0.b, p0/m, wsp mov z0.b, wsp mov z0.d, p0/m, sp mov z0.d, sp insert stray symbols into the symbol table.
2017-11-13gas/ia64: fix testsuite failuresJan Beulich
Commit dd90581873 ("Place .shstrtab section after .symtab and .strtab, thus restoring monotonically incre... ") adjusted section numbers, but forgot to adjust sh_link references from relocation and group section table entries. Additionally some other (perhaps subsequent) change appears to have added .rel.* and .rela.* sections to their respective groups, which requires some further adjustments to group-2.d. I assume this additional breakage wasn't noticed because the test was already failing at that time. This makes the gas testsuite complete successfully again for me in a cross build on ix86-linux; there continue to be quite a few ld failures.
2017-11-13x86: don't default variable shift count insns to 8-bit operand sizeJan Beulich
Just like %dx in I/O instructions isn't suitable to derive operand size information, %cl source operands of shift instructions aren't.
2017-11-13x86/Intel: don't mistake riz/eiz as base registerJan Beulich
Just like we make rsp/esp a base register even if it comes second, make riz/eiz an index register even if it comes first.
2017-11-13x86-64/Intel: issue diagnostic for out of range displacementJan Beulich
... rather than silently dropping it altogether. i386_finalize_displacement() expects baseindex to already be set, so the respective statement needs to be moved up. This then also allows a subsequent conditional to be simplified. For this to not regress on 32-bit addressing, break out address size guessing from i386_index_check(), invoking the new function earlier so that i386_finalize_displacement() has i.prefix[ADDR_PREFIX] available. i386_addressing_mode () in turn needs i.base_reg / i.index_reg set earlier.
2017-11-09Fix riscv dwarf2-10 gas testsuite failure.Jim Wilson
gas/ * testsuite/gas/elf/dwarf2-10.l: Accept optional line number in error.
2017-11-09Enable the Dot Product extension by default for Armv8.4-a.Tamar Christina
include/ * opcode/aarch64.h (AARCH64_ARCH_V8_4): Enable DOTPROD. gas/testsuite * gas/aarch64/dotproduct_armv8_4.s: New. * gas/aarch64/dotproduct_armv8_4.d: New.
2017-11-09Add assembler and disassembler support for the new Armv8.4-a registers for ↵Tamar Christina
AArch64. Some of these instructions have been back-ported as optional extensions to Armv8.2-a and higher, but others are only available for Armv8.4-a. opcodes/ * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers; dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2, cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2, sder32_el2, vncr_el2. (aarch64_sys_reg_supported_p): Likewise. (aarch64_pstatefields): Add dit register. (aarch64_pstatefield_supported_p): Likewise. (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os, vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os, vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1, rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os, rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1, ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os, rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os. gas/testsuite * gas/aarch64/armv8_4-a-registers-illegal.d: New. * gas/aarch64/armv8_4-a-registers-illegal.l: New. * gas/aarch64/armv8_4-a-registers-illegal.s: New. * gas/aarch64/armv8_4-a-registers.d: New. * gas/aarch64/armv8_4-a-registers.s: New.
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina
gas/ * config/tc-aarch64.c (process_omitted_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2 and AARCH64_OPND_IMM_2. (parse_operands): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2, AARCH64_OPND_IMM_2, AARCH64_OPND_MASK and AARCH64_OPND_ADDR_OFFSET. include/ * opcode/aarch64.h: (aarch64_opnd): Add AARCH64_OPND_Va, AARCH64_OPND_MASK, AARCH64_OPND_IMM_2, AARCH64_OPND_ADDR_OFFSET and AARCH64_OPND_SM3_IMM2. (aarch64_insn_class): Add cryptosm3 and cryptosm4. (arch64_feature_set): Make uint64_t. opcodes/ * aarch64-asm.h (ins_addr_offset): New. * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3. (aarch64_ins_addr_offset): New. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_addr_offset): New. * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3. (aarch64_ext_addr_offset): New. * aarch64-dis-2.c: Regenerate. * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2, FLD_imm4_2 and FLD_SM3_imm2. * aarch64-opc.c (fields): Add FLD_imm6_2, FLD_imm4_2 and FLD_SM3_imm2. (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET. (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2, AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET. * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New. * aarch64-tbl.h (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
2017-11-09Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own ↵Tamar Christina
options (+aes and +sha2). The reason for the split is because with the introduction of Armv8.4-a the implementation of AES has explicitly been made independent of the implementation of the other crypto extensions. gas * config/tc-aarch64.c (aarch64_arch_option_table): Add armv8.4-a. (aarch64_features): Added SM4 and SHA3. include * opcode/aarch64.h: (AARCH64_FEATURE_V8_4, AARCH64_FEATURE_SM4): New. (AARCH64_ARCH_V8_4, AARCH64_FEATURE_SHA3): New. opcodes * aarch64-tbl.h (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New. (aarch64_feature_sm4, aarch64_feature_sha3): New. (aarch64_feature_fp_16_v8_2): New. (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New. (V8_4_INSN, CRYPTO_V8_2_INSN): New. (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
2017-11-08Fix typo in changelogNick Clifton
2017-11-08Split the AArch64 Crypto instructions for AES and SHA1+2 into their own ↵Nick Clifton
options (+aes and +sha2). The new options are: +aes: Enables the AES instructions of Armv8-a, enabled by default with +crypto. +sha2: Enables the SHA1 and SHA2 instructions of Armv8-a, enabled by default with +crypto. These options have been turned on by default when +crypto is used, as such no breakage is expected. The reason for the split is because with the introduction of Armv8.4-a the implementation of AES has explicitly been made independent of the implementation of the other crypto extensions. Backporting the split does not break any of the previous requirements and so is safe to do. gas * config/tc-aarch64.c (aarch64_features): Include AES and SHA2 in CRYPTO. Add SHA2 and AES. include * opcode/aarch64.h: (AARCH64_FEATURE_SHA2, AARCH64_FEATURE_AES): New. opcodes * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2. (aarch64_feature_sha2, aarch64_feature_aes): New. (SHA2, AES): New. (AES_INSN, SHA2_INSN): New. (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS. (sha1h, sha1su1, sha256su0, sha1c, sha1p, sha1m, sha1su0, sha256h, sha256h2, sha256su1): Change to SHA2_INS.
2017-11-08Adds command line support for Armv8.4-A, via the new command line option ↵Jiong Wang
-march=armv8.4-a. Add support for "+dotprod" ARM feature (required for ARMv8.4-A). Add assembler and disassembler support for new FP16 instructions introduced in Armv8.4-A gas * config/tc-arm.c (arm_extensions): (arm_archs): New entry for "armv8.4-a". Add FPU_ARCH_DOTPROD_NEON_VFP_ARMV8. (arm_ext_v8_2): New variable. (enum arm_reg_type): New enumeration REG_TYPE_NSD. (reg_expected_msgs): New entry for REG_TYPE_NSD. (parse_typed_reg_or_scalar): Handle REG_TYPE_NSD. (parse_scalar): Support REG_TYPE_VFS. (enum operand_parse_code): New enumerations OP_RNSD and OP_RNSD_RNSC. (parse_operands): Handle OP_RNSD and OP_RNSD_RNSC. (NEON_SHAPE_DEF): New entries for DHH and DHS. (neon_scalar_for_fmac_fp16_long): New function to generate Rm encoding for new FP16 instructions in ARMv8.2-A. (do_neon_fmac_maybe_scalar_long): New function to encode new FP16 instructions in ARMv8.2-A. (do_neon_vfmal): Wrapper function for vfmal. (do_neon_vfmsl): Wrapper function for vfmsl. (insns): New entries for vfmal and vfmsl. * doc/c-arm.texi (-march): Document "armv8.4-a". * testsuite/gas/arm/dotprod-mandatory.d: New test. * testsuite/gas/arm/armv8_2-a-fp16.s: New test source. * testsuite/gas/arm/armv8_2-a-fp16-illegal.s: New test source. * testsuite/gas/arm/armv8_2-a-fp16.d: New test. * testsuite/gas/arm/armv8_3-a-fp16.d: New test. * testsuite/gas/arm/armv8_4-a-fp16.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-thumb2.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-illegal.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-illegal.l: New error file. opcodes * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new FP16 instructions, including vfmal.f16 and vfmsl.f16. include * opcode/arm.h (ARM_AEXT2_V8_4A): Include Dot Product feature. (ARM_EXT2_V8_4A): New macro. (ARM_AEXT2_V8_4A): Likewise. (ARM_ARCH_V8_4A): Likewise.
2017-11-08xtensa message pluralizationAlan Modra
* config/tc-xtensa.c (finish_vinsn): Properly pluralize error message.
2017-11-07RISC-V: Fix riscv g++ testsuite EH failures.Jim Wilson
This fixes some EH failures for the medany code model in the g++ testsuite. The problem is that the assembler is computing some values in the eh_frame section as constants, that instead should have had relocs to be resolved by the linker. This happens in output_cfi_insn in the DW_CFA_advance_loc case where it compares label frags and immediately simplifies if they are the same. We can fix that by forcing a new frag after every instruction that the linker can reduce in size. I've also added a testcase to verify the fix. This was tested with binutils make check, and gcc/g++ make checks on qemu for medlow and medany code models. gas/ * config/tc-riscv.c (append_insn): Call frag_wane and frag_new at end for linker optimizable relocs. * testsuite/gas/riscv/eh-relocs.d: New. * testsuite/gas/riscv/eh-relocs.s: New. * testsuite/gas/riscv/riscv.exp: Run eh-relocs test.
2017-11-07RISC-V: Add satp as an alias for sptbrPalmer Dabbelt
The RISC-V privileged ISA changed the name of sptbr (Supervisor Page Table Base Register) to satp (Supervisor Address Translation and Protection) to reflect the fact it could be used for more than just paging. This patch adds an alias, as they're the same register. include/ChangeLog 2017-11-06 Palmer Dabbelt <palmer@dabbelt.com> * opcode/riscv-opc.h (sptbr): Rename to satp. (CSR_SPTBR): Rename to CSR_SATP. (sptbr): Alias to CSR_SATP. gas/ChangeLog 2017-11-06 Palmer Dabbelt <palmer@dabbelt.com> * testsuite/gas/riscv/satp.d: New test. testsuite/gas/riscv/satp.s: Likewise. testsuite/gas/riscv/riscv.exp: Likewise. config/tc-riscv.c (md_begin): Handle CSR aliases.
2017-11-07This patch similarly to the AArch64 one enables Dot Product support by ↵Tamar Christina
default for the Cortex-A55 and Cortex-A75 which have hardware support for these instructions. gas * config/tc-arm.c (arm_cpus): Change FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 into FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD. include * opcode/arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD): New macro.
2017-11-07bundle_lock message tidyAlan Modra
I'd edited these thinking that there might be cases where the counts were one, but on further investigation it appears not. What's left here are some minor tweaks. * read.c (assemble_one, s_bundle_unlock): Formatting. Consistently add comma and "bytes" to error message. * testsuite/gas/i386/bundle-bad.l: Adjust to suit.
2017-11-07readelf ngettext fixesAlan Modra
This patch is a first pass at fixing readelf message pluralization. I've deliberately not fixed the "out of memory" errors since it's very unlikely that they will ever be complaining about not being able to allocate for a single entry, and a few others where the size is very unlikely to be 1 byte. Then there are messages like this one: "Out of %lu items there are %zu bucket clashes (longest of %zu entries).\n" I suppose this could be split into three parts, "Of %lu items ", "there are %zu bucket clashes ", and "(longest of %zu entries).\n", each part being printed separately, but that might not be ideal for sentence construction in other languages. For now I'm punting on this one. Changes to readelf output require lots of testsuite adjustment.. binutils/ * dwarf.c (read_uleb128): Properly pluralize messages. (display_debug_lines_raw, display_debug_loc): Likewise. (display_debug_names, process_cu_tu_index): Likewise. * od-macho.c (dump_code_signature_superblob): Likewise. * readelf.c (process_program_headers): Likewise. (process_section_header, process_relocs): Likewise. (hppa_process_unwind, arm_process_unwind): Likewise. (process_dynamic_section, process_version_sections): Likewise. (process_symbol_table, process_syminfo): Likewise. (apply_relocations, process_mips_specific): Likewise. (process_gnu_liblist, process_notes_at): Likewise. (process_archive): Likewise. * testsuite/binutils-all/dw2-1.W, * testsuite/binutils-all/dw2-3.W, * testsuite/binutils-all/dw2-3gabi.W, * testsuite/binutils-all/dw5.S, * testsuite/binutils-all/dw5.W, * testsuite/binutils-all/i386/compressed-1a.d, * testsuite/binutils-all/libdw2-compressedgabi.out, * testsuite/binutils-all/objdump.W, * testsuite/binutils-all/readelf.r, * testsuite/binutils-all/readelf.r-64, * testsuite/binutils-all/x86-64/compressed-1a.d: Update for pluralization fixes. gas/ * testsuite/gas/arm/got_prel.d, * testsuite/gas/elf/dwarf2-1.d, * testsuite/gas/elf/dwarf2-2.d, * testsuite/gas/elf/dwarf2-3.d, * testsuite/gas/elf/dwarf2-5.d, * testsuite/gas/elf/dwarf2-6.d, * testsuite/gas/i386/debug1.d, * testsuite/gas/i386/dw2-compress-1.d, * testsuite/gas/i386/dw2-compress-3a.d, * testsuite/gas/i386/dw2-compress-3b.d, * testsuite/gas/i386/dw2-compressed-1.d, * testsuite/gas/i386/dw2-compressed-3a.d, * testsuite/gas/i386/dw2-compressed-3b.d, * testsuite/gas/i386/ilp32/x86-64-localpic.d, * testsuite/gas/i386/localpic.d, * testsuite/gas/i386/x86-64-localpic.d, * testsuite/gas/ia64/pr13167.d, * testsuite/gas/mips/loc-swap-2.d, * testsuite/gas/mips/loc-swap.d, * testsuite/gas/mips/micromips@loc-swap-2.d, * testsuite/gas/mips/micromips@loc-swap.d, * testsuite/gas/mips/mips16-dwarf2-n32.d, * testsuite/gas/mips/mips16-dwarf2.d, * testsuite/gas/mips/mips16@loc-swap-2.d, * testsuite/gas/mips/mips16@loc-swap.d, * testsuite/gas/mips/mips16e@loc-swap.d, * testsuite/gas/mmix/bspec-1.d, * testsuite/gas/mmix/bspec-2.d, * testsuite/gas/tic6x/unwind-1.d, * testsuite/gas/tic6x/unwind-2.d, * testsuite/gas/tic6x/unwind-3.d: Update for pluralization fixes. ld/ * testsuite/ld-aarch64/ifunc-13.d, * testsuite/ld-aarch64/ifunc-15.d, * testsuite/ld-aarch64/ifunc-20.d, * testsuite/ld-alpha/tlsbin.rd, * testsuite/ld-alpha/tlspic.rd, * testsuite/ld-arm/ifunc-3.rd, * testsuite/ld-arm/ifunc-9.rd, * testsuite/ld-arm/unwind-mix.d, * testsuite/ld-arm/unwind-rel.d, * testsuite/ld-cris/hiddef1.d, * testsuite/ld-cris/libdso-13.d, * testsuite/ld-cris/libdso-2.d, * testsuite/ld-cris/pr16044.d, * testsuite/ld-cris/tls-local-63.d, * testsuite/ld-cris/tls-local-64.d, * testsuite/ld-cris/tls-und-38.d, * testsuite/ld-cris/tls-und-42.d, * testsuite/ld-cris/tls-und-46.d, * testsuite/ld-cris/tls-und-50.d, * testsuite/ld-cris/weakref3.d, * testsuite/ld-cris/weakref4.d, * testsuite/ld-elf/comm-data2r.rd, * testsuite/ld-elf/discard1.d, * testsuite/ld-elf/discard2.d, * testsuite/ld-elf/pr19539.d, * testsuite/ld-elf/pr22374-1.r, * testsuite/ld-elf/pr22374-2.r, * testsuite/ld-i386/combreloc.d, * testsuite/ld-i386/emit-relocs-nacl.rd, * testsuite/ld-i386/emit-relocs.rd, * testsuite/ld-i386/pr13302.d, * testsuite/ld-i386/pr17709-nacl.rd, * testsuite/ld-i386/pr17709.rd, * testsuite/ld-i386/pr19539.d, * testsuite/ld-i386/pr19615.d, * testsuite/ld-i386/pr19636-1a.d, * testsuite/ld-i386/pr19636-1e.d, * testsuite/ld-i386/pr19636-1f.d, * testsuite/ld-i386/pr19636-2a.d, * testsuite/ld-i386/pr19636-2b.d, * testsuite/ld-i386/pr19636-2d-nacl.d, * testsuite/ld-i386/pr19636-2e-nacl.d, * testsuite/ld-i386/pr19636-3a.d, * testsuite/ld-i386/pr19636-3d.d, * testsuite/ld-i386/pr19636-3e.d, * testsuite/ld-i386/pr19636-4a.d, * testsuite/ld-i386/pr19645.d, * testsuite/ld-i386/pr19827-nacl.rd, * testsuite/ld-i386/pr19827.rd, * testsuite/ld-i386/pr20253-4a.d, * testsuite/ld-i386/pr20253-4b.d, * testsuite/ld-i386/pr20253-5.d, * testsuite/ld-i386/tlsbin-nacl.rd, * testsuite/ld-i386/tlsbin.rd, * testsuite/ld-i386/tlspic-nacl.rd, * testsuite/ld-i386/tlspic.rd, * testsuite/ld-i386/undefweakb.d, * testsuite/ld-ia64/tlsbin.rd, * testsuite/ld-ia64/tlspic.rd, * testsuite/ld-ifunc/ifunc-13-i386.d, * testsuite/ld-ifunc/ifunc-13-x86-64.d, * testsuite/ld-ifunc/ifunc-15-i386.d, * testsuite/ld-ifunc/ifunc-15-x86-64.d, * testsuite/ld-ifunc/ifunc-20-i386.d, * testsuite/ld-ifunc/ifunc-20-x86-64.d, * testsuite/ld-ifunc/ifunc-23a-x86.d, * testsuite/ld-ifunc/ifunc-23b-x86.d, * testsuite/ld-ifunc/ifunc-23c-x86.d, * testsuite/ld-ifunc/ifunc-24a-x86.d, * testsuite/ld-ifunc/ifunc-24b-x86.d, * testsuite/ld-ifunc/ifunc-24c-x86.d, * testsuite/ld-ifunc/ifunc-25a-x86.d, * testsuite/ld-ifunc/ifunc-25b-x86.d, * testsuite/ld-ifunc/ifunc-25c-x86.d, * testsuite/ld-m68k/got-1.d, * testsuite/ld-mips-elf/vxworks1.rd, * testsuite/ld-powerpc/ambiguousv1.d, * testsuite/ld-powerpc/ambiguousv1b.d, * testsuite/ld-powerpc/ambiguousv2.d, * testsuite/ld-powerpc/ambiguousv2b.d, * testsuite/ld-powerpc/tlsexe.r, * testsuite/ld-powerpc/tlsexe32.r, * testsuite/ld-powerpc/tlsexetoc.r, * testsuite/ld-powerpc/tlsso.r, * testsuite/ld-powerpc/tlsso32.r, * testsuite/ld-powerpc/tlstocso.r, * testsuite/ld-powerpc/vle-multiseg-1.d, * testsuite/ld-powerpc/vle-multiseg-2.d, * testsuite/ld-powerpc/vle-multiseg-3.d, * testsuite/ld-s390/tlsbin.rd, * testsuite/ld-s390/tlsbin_64.rd, * testsuite/ld-s390/tlspic.rd, * testsuite/ld-s390/tlspic_64.rd, * testsuite/ld-sh/ld-r-1.d, * testsuite/ld-sh/sh64/gotplt.d, * testsuite/ld-sh/shared-1.d, * testsuite/ld-sh/tlsbin-2.d, * testsuite/ld-sh/tlspic-2.d, * testsuite/ld-sparc/gotop32.rd, * testsuite/ld-sparc/gotop64.rd, * testsuite/ld-sparc/tlssunpic32.rd, * testsuite/ld-sparc/tlssunpic64.rd, * testsuite/ld-sparc/vxworks1-lib.rd, * testsuite/ld-tic6x/shlib-app-1.rd, * testsuite/ld-tic6x/shlib-app-1b.rd, * testsuite/ld-tic6x/shlib-app-1r.rd, * testsuite/ld-tic6x/shlib-app-1rb.rd, * testsuite/ld-tic6x/shlib-noindex.rd, * testsuite/ld-vax-elf/export-class-data.rd, * testsuite/ld-x86-64/pr13082-1a.d, * testsuite/ld-x86-64/pr13082-1b.d, * testsuite/ld-x86-64/pr13082-2a.d, * testsuite/ld-x86-64/pr13082-2b.d, * testsuite/ld-x86-64/pr13082-3a.d, * testsuite/ld-x86-64/pr13082-3c.d, * testsuite/ld-x86-64/pr13082-4a.d, * testsuite/ld-x86-64/pr13082-5a.d, * testsuite/ld-x86-64/pr13082-5b.d, * testsuite/ld-x86-64/pr13082-6a.d, * testsuite/ld-x86-64/pr13082-6b.d, * testsuite/ld-x86-64/pr17709-nacl.rd, * testsuite/ld-x86-64/pr17709.rd, * testsuite/ld-x86-64/pr19539a.d, * testsuite/ld-x86-64/pr19539b.d, * testsuite/ld-x86-64/pr19615.d, * testsuite/ld-x86-64/pr19636-1a.d, * testsuite/ld-x86-64/pr19636-1d.d, * testsuite/ld-x86-64/pr19636-1e.d, * testsuite/ld-x86-64/pr19636-2a.d, * testsuite/ld-x86-64/pr19636-2e.d, * testsuite/ld-x86-64/pr19636-2f.d, * testsuite/ld-x86-64/pr19636-3a.d, * testsuite/ld-x86-64/pr19645.d, * testsuite/ld-x86-64/pr19807-2b.d, * testsuite/ld-x86-64/pr19807-2d.d, * testsuite/ld-x86-64/pr19827-nacl.rd, * testsuite/ld-x86-64/pr19827.rd, * testsuite/ld-x86-64/pr20253-4a.d, * testsuite/ld-x86-64/pr20253-4b.d, * testsuite/ld-x86-64/pr20253-4d.d, * testsuite/ld-x86-64/pr20253-4e.d, * testsuite/ld-x86-64/pr20253-5a.d, * testsuite/ld-x86-64/pr20253-5b.d, * testsuite/ld-x86-64/tlsbin-nacl.rd, * testsuite/ld-x86-64/tlsbin.rd, * testsuite/ld-x86-64/tlspic-nacl.rd, * testsuite/ld-x86-64/tlspic.rd, * testsuite/ld-x86-64/tlspic2-nacl.rd: Update for pluralization fixes.
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