diff options
| author | Tamar Christina <tamar.christina@arm.com> | 2018-07-06 16:18:19 +0100 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2018-07-06 16:29:42 +0100 |
| commit | e04c0868e452b7a2b02331a0262a77e50d477a9c (patch) | |
| tree | 70484aea9730fb37ea6dec2297a7f750a1e876d8 | |
| parent | 96e59904744c200362cbe841a1607075d53f424a (diff) | |
Fix SBO bit in disassembly mask for ldrah on AArch64.
The disassembly mask for ldarh incorrectly didn't mask out bit 20 which
is part of the SBO part of the instruction and shouldn't be considered input.
This fixes the wrong bit fixing the disassembly of instructions to
ldarh and makes the behavior consistent.
opcodes/
PR binutils/23242
* aarch64-tbl.h (ldarh): Fix disassembly mask.
(cherry picked from commit f311ba7ed84d66ae2cd77bd969747d7ab959d866)
Signed-off-by: Tamar Christina <tamar.christina@arm.com>
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 5689da0333..cf1f0523a9 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2018-07-06 Tamar Christina <tamar.christina@arm.com> + PR binutils/23242 + * aarch64-tbl.h (ldarh): Fix disassembly mask. + +2018-07-06 Tamar Christina <tamar.christina@arm.com> + PR binutils/23369 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1, vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1. diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index c720fea511..559efdba23 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -3219,7 +3219,7 @@ struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("ldxrh", 0x485f7c00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), CORE_INSN ("ldaxrh", 0x485ffc00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), CORE_INSN ("stlrh", 0x489ffc00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), - CORE_INSN ("ldarh", 0x48dffc00, 0xffeffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), + CORE_INSN ("ldarh", 0x48dffc00, 0xfffffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), CORE_INSN ("stxr", 0x88007c00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q), CORE_INSN ("stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q), CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q), |